Anna Wong

US Patent:

20060195496, Aug 31, 2006

Filed:

May 12, 2006

Appl. No.:

11/432846

Inventors:

Vasisht Vadi - San Jose CA, US
Jennifer Wong - Fremont CA, US
Bernard New - Carmel Valley CA, US
Alvin Ching - Sunnyvale CA, US
John Thendean - Berkeley CA, US
Anna Wong - Santa Clara CA, US
James Simkins - Park City UT, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 15/00

US Classification:

708200000

Abstract:

An integrated circuit for pattern detection including: an arithmetic logic unit coupled to a comparison circuit, where the arithmetic logic unit is programmed by an opcode; a selected pattern of a plurality of patterns selected by a first multiplexer, where the first multiplexer is coupled to the comparison circuit; and a register coupled to the comparison circuit for storing at least a partial comparison between an output of the arithmetic logic unit and the selected pattern.

US Patent:

20060230092, Oct 12, 2006

Filed:

May 12, 2006

Appl. No.:

11/433369

Inventors:

Alvin Ching - Sunnyvale CA, US
Jennifer Wong - Fremont CA, US
Bernard New - Carmel Valley CA, US
James Simkins - Park City UT, US
John Thendean - Berkeley CA, US
Anna Wong - Santa Clara CA, US
Vasisht Vadi - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 7/38

US Classification:

708490000

Abstract:

A physical floorplan for a digital signal processing (DSP) block including; an interconnect column having a plurality of programmable interconnect elements; a first DSP element having a plurality of first columns, a first output register column of the plurality of first columns positioned adjacent to the interconnect column; and a second DSP element, having a plurality of second columns a second output register column of the plurality of second columns positioned adjacent to the interconnect column.

US Patent:

20060230096, Oct 12, 2006

Filed:

May 12, 2006

Appl. No.:

11/433517

Inventors:

John Thendean - , US
Jennifer Wong - Fremont CA, US
Bernard New - Carmel Valley CA, US
Alvin Ching - Sunnyvale CA, US
James Simkins - Park City UT, US
Anna Wong - Santa Clara CA, US
Vasisht Vadi - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 7/50

US Classification:

708700000

Abstract:

An integrated circuit having a digital signal processing (DSP) circuit is disclosed. The DSP circuit includes: a plurality of multiplexers receiving a first set, second set, and third set of input data bits, where the plurality of multiplexers are coupled to a first opcode register; a bitwise adder coupled to the plurality of multiplexers for generating a sum set of bits and a carry set of bits from bitwise adding together the first, second, and third set of input data bits; and a second adder coupled to the bitwise adder for adding together the sum set of bits and carry set of bits to produce a summation set of bits and a plurality of carry-out bits, where the second adder is coupled to a second opcode register.

US Patent:

20060288070, Dec 21, 2006

Filed:

May 12, 2006

Appl. No.:

11/433332

Inventors:

Vasisht Vadi - San Jose CA, US
Jennifer Wong - Fremont CA, US
Bernard New - Carmel Valley CA, US
Alvin Ching - Sunnyvale CA, US
John Thendean - Berkeley CA, US
Anna Wong - Santa Clara CA, US
James Simkins - Park City UT, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 7/38

US Classification:

708524000

Abstract:

A method for detecting a pattern from an arithmetic logic unit (ALU) in an integrated circuit. The method includes the steps of: generating an output from an ALU; bitwise comparing the ALU output to a pattern to produce a first output; inverting the pattern and comparing the ALU output with the inverted pattern to produce a second output; bitwise masking the first and second outputs using a mask of a plurality of masks to produce third and fourth output bits; combining the third and fourth output bits to produce first and a second output comparison bits; and storing the first and second output comparison bits in a memory.