FREESCALE SEMICONDUCTOR Austin, TX Jul 2010 to Jan 2011 Senior Compiler Engineer level IVSUN MICROSYSTEMS INCORPORATED Menlo Park, CA Jul 2009 to Jun 2010Senior Software Engineer (SW) May 1999 to Sep 2008Qualcomm
May 1998 to Apr 1999 Consultant EngineerMOTOROLA INDIA LIMITED Bangalore, Karnataka Jan 1998 to May 1998INDIA , Member of Technical StaffBangalore, Karnataka Jan 1997 to Jan 1998MECON INDIA LTD
Oct 1987 to Dec 1993 Processor Architecture, Compilers
Education:
Indian Institute of Science Bangalore, Karnataka Jan 1997 Computer Science
Anoop Kumar - Mountain View CA, US Sreekumar Ramakrishnan Nair - Sunnyvale CA, US
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
G06F 9/45
US Classification:
717151, 717144, 717156
Abstract:
The present invention describes a method of efficiently optimizing instruction scheduling and register allocation in a post optimizer. The method removes false register dependencies between pipelined instructions by building an incremental (partial) interference graph of register allocation for scheduled instructions. False dependency graph indicates the amount of parallelism in the data flow graph. The incremental interference graph uses a mix of virtual and physical registers. The interference graph is built incrementally as an instruction schedular schedules each instruction. The optimization is done incrementally on localized code. The physical register mapping is maximized and virtual registers are created on demand basis.
Egon Zenhder - Associate IM (2012) Bhartiya Vidya Bhavan - Faculty (2008) Modi Pharma Pvt Ltd. - Sales Cordinator (2011-2011)
Education:
IGNOU - MCA, Jamia Hamdard - BCA, DOEACC - O Level, DOEACC - A level
About:
Hi my self Anoop Kumar I am gradute in BCA from jamia university and doeacc holder I m very frienly nature guy…. And fun loving guyI love dancing, singing , playing badminton ets…