Anthony Joseph Calderone

US Patent:

6594610, Jul 15, 2003

Filed:

May 11, 2001

Appl. No.:

09/853351

Inventors:

Shahin Toutounchi - Pleasanton CA
Anthony P. Calderone - Soquel CA
Zhi-Min Ling - Cupertino CA
Robert D. Patrie - Scotts Valley CA
Eric J. Thorne - Santa Cruz CA
Robert W. Wells - Cupertino CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 1900

US Classification:

702117, 702 58, 702123, 702183, 703 14, 703 27, 714 2, 714 30, 714 39, 714725, 716 4, 716 17

Abstract:

A new testing method uses a field programmable gate array to emulate faults, instead of using a separate computer to simulate faults. In one embodiment, a few (e. g. , two or three) known good FPGAs are selected. A fault is introduced into the design of a FPGA configuration. The configuration is loaded into the FPGAs. A test vector is applied and the result is evaluated. If the result is different from that of a fault-free configuration, the fault is caught. One application of this method is to evaluate fault coverage. A fault model that can be used in the present invention is disclosed.