Anthony M Coyle

US Patent:

6489178, Dec 3, 2002

Filed:

Jan 19, 2001

Appl. No.:

09/766195

Inventors:

Anthony L. Coyle - Plano TX
George A. Bednarz - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2100

US Classification:

438 51, 438 64, 438127, 257415, 257433, 26427217

Abstract:

A plastic land-grid array package, a ball-grid array package, and a plastic leaded package for micromechanical components are fabricated by a molding process characterized by lining the cavity surfaces of the top and bottom mold halves with a protective plastic film, which also protects the surfaces of the components during the molding phase, selectively encapsulating the bonding pads and coupling members of the chip while leaving empty space above the components, and attaching a lid over the components. A molding method as well as a molding apparatus are provided compatible with the sensitivity of the micromechanical devices, yet flexible with regard to the technique used to assemble the chip and the substrate. Furthermore, the method disclosed is flexible with regard to the material and the properties of the substrate. It is an aspect of the present invention to be applicable to a variety of different semiconductor micromechanical devices, for instance actuators, motors, sensors, spatial light modulators, and deformable mirror devices.

US Patent:

6518089, Feb 11, 2003

Filed:

Feb 2, 2001

Appl. No.:

09/776465

Inventors:

Anthony L. Coyle - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2144

US Classification:

438106

Abstract:

A robust, low inductance electronic package for small area semiconductor chips is provided which includes a flexible polymer film having electronic circuitry on one or more major surfaces, a bumped flip chip integrated circuit attached to the first surface, an array of solder balls to the second surface, and the device encapsulated in a plastic molding compound. An assembly and packaging method is disclosed wherein multiple devices are encapsulated simultaneously on a continuous polymer film, thereby providing a method compatible with high volume and low cost manufacturing processes and equipment.

US Patent:

6541832, Apr 1, 2003

Filed:

Jan 19, 2001

Appl. No.:

09/766197

Inventors:

Anthony L. Coyle - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2978

US Classification:

257415, 257416

Abstract:

Low-cost plastic cavity-up land-grid array packages and ball-grid array packages are provided, suitable for wire-bonded chips having micromechanical components. The packages feature a thermal heat spreader and a protective lid. The package structure disclosed is flexible with regard to materials and geometrical detail, and provides solutions to specific functions such as storage space for chemical compounds within the enclosed cavity of the package.

US Patent:

6586676, Jul 1, 2003

Filed:

May 15, 2001

Appl. No.:

09/855879

Inventors:

Samuel D. Pritchett - Flower Mound TX
Anthony L. Coyle - Plano TX
Milton L. Buschbom - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2328

US Classification:

174 522, 174 524, 174260, 361761, 361763, 361792

Abstract:

A semiconductor device has passive components integrated with the circuit and encapsulated in a plastic package for solder ball or leaded attachment. A plastic chip-scale semiconductor device has a substrate made of a plurality of patterned insulating layers alternating with patterned electrically conductive layers, the layers mutually adhering to form the substrate. The layers include a plurality of passive electrical components, such as capacitors, inductors, and resistors, and routing lines. Most routing lines terminate in a first plurality of bondable contact pads and a second plurality of solderable contact pads. The components and lines form a web and are configured mostly in a narrow peripheral band at least partially around a central substrate area, and are operable with high performance in conjunction with an integrated circuit (IC) chip. The chip is attached to the central substrate area and electrically connected to the first plurality of contact pads, respectively, whereby the passive components are integrated with the IC. Plastic encapsulation material surrounds the chip, first plurality of contact pads, and passive components such that the outline of the material is approximately the same as the outline of the chip.

US Patent:

6696757, Feb 24, 2004

Filed:

Jun 24, 2002

Appl. No.:

10/178138

Inventors:

Mohammad Yunus - Dallas TX
Anthony L. Coyle - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2348

US Classification:

257735, 257696, 257738, 257758, 257778, 257784

Abstract:

A metallurgical interconnection for electronic devices is described, wherein the interconnection has first and second interconnection metals. The first metal is shaped to enlarge the contact area, thus providing maximum mechanical interconnection strength, and to stop nascent cracks, which propagate in the interconnection. Preferred shapes include castellation and corrugation. The castellation may include metal protrusions, which create wall-like obstacles in the interconnection zones of highest thermomechanical stress, whereby propagating cracks are stopped. The surface of the first metal has an affinity to form metallurgical contacts. The second metal is capable of reflowing. The first metal is preferably copper, and the second metal tin or a tin alloy.

US Patent:

6753616, Jun 22, 2004

Filed:

Dec 16, 2002

Appl. No.:

10/320585

Inventors:

Anthony L. Coyle - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2328

US Classification:

257787, 257778

Abstract:

A robust, low inductance electronic package for small area semiconductor chips is provided which includes a flexible polymer film having electronic circuitry on one or more major surfaces, a bumped flip chip integrated circuit attached to the first surface, an array of solder balls to the second surface, and the device encapsulated in a plastic molding compound. An assembly and packaging method is disclosed wherein multiple devices are encapsulated simultaneously on a continuous polymer film, thereby providing a method compatible with high volume and low cost manufacturing processes and equipment.

US Patent:

6858910, Feb 22, 2005

Filed:

Oct 16, 2002

Appl. No.:

10/271815

Inventors:

Anthony L. Coyle - Plano TX, US
George A. Bednarz - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L029/82

US Classification:

257415, 257417, 26427217, 438 51, 438127

Abstract:

A plastic land-grid array package, a ball-grid array package, and a plastic leaded package for micromechanical components are fabricated by a molding process characterized by lining the cavity surfaces of the top and bottom mold halves with a protective plastic film, which also protects the surfaces of the components during the molding phase, selectively encapsulating the bonding pads and coupling members of the chip while leaving empty space above the components, and attaching a lid over the components. A molding method as well as a molding apparatus are provided compatible with the sensitivity of the micromechanical devices, yet flexible with regard to the technique used to assemble the chip and the substrate. Furthermore, the method disclosed is flexible with regard to the material and the properties of the substrate. It is an aspect of the present invention to be applicable to a variety of different semiconductor micromechanical devices, for instance actuators, motors, sensors, spatial light modulators, and deformable mirror devices.

US Patent:

6916689, Jul 12, 2005

Filed:

Apr 21, 2003

Appl. No.:

10/419408

Inventors:

Samuel D. Pritchett - Flower Mound TX, US
Anthony L. Coyle - Plano TX, US
Milton L. Buschbom - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L021/44
H01L021/48

US Classification:

438126, 438127, 174 524

Abstract:

A semiconductor device has passive components integrated with the circuit and encapsulated in a plastic package for solder ball or leaded attachment. A plastic chip-scale semiconductor device has a substrate made of a plurality of patterned insulating layers alternating with patterned electrically conductive layers, the layers mutually adhering to form the substrate. The layers include a plurality of passive electrical components, such as capacitors, inductors, and resistors, and routing lines. Most routing lines terminate in a first plurality of bondable contact pads and a second plurality of solderable contact pads. The components and lines form a web and are configured mostly in a narrow peripheral band at least partially around a central substrate area, and are operable with high performance in conjunction with an integrated circuit (IC) chip. The chip is attached to the central substrate area and electrically connected to the first plurality of contact pads, respectively, whereby the passive components are integrated with the IC. Plastic encapsulation material surrounds the chip, first plurality of contact pads, and passive components such that the outline of the material is approximately the same as the outline of the chip.