Anthony Dip

US Patent:

6799940, Oct 5, 2004

Filed:

Dec 5, 2002

Appl. No.:

10/310141

Inventors:

Raymond Joe - Austin TX
Anthony Dip - Cedar Creek TX

Assignee:

Tokyo Electron Limited - Tokyo

International Classification:

B65G 4907

US Classification:

414937, 414935, 901 30

Abstract:

A removable semiconductor wafer susceptor used for supporting a substrate during batch processing. The susceptor includes a flat circular central plane with a predetermined outer diameter. The susceptor is sized to fit within an inner diameter formed from wafer support ledges of a wafer transport container. The susceptor includes edges that are chamfered and rounded to lessen stress concentration at the edges. The susceptor is transported through processing by a sieving action of transport automation.

US Patent:

6869892, Mar 22, 2005

Filed:

Jan 30, 2004

Appl. No.:

10/767470

Inventors:

Keisuke Suzuki - Tokyo-to, JP
Toshiyuki Ikeuchi - Tokyo-to, JP
Kimiya Aoki - Tokyo-to, JP
David Paul Brunco - San Jose CA, US
Steven Robert Soss - San Jose CA, US
Anthony Dip - Cedar Creek TX, US

Assignee:

Tokyo Electron Limited - Tokyo-To
Intel Corporation - Santa Clara CA

International Classification:

H01L021/31

US Classification:

438770, 438771, 438773, 438694, 438735, 438738, 438769, 438787

Abstract:

A method of oxidizing work pieces according to the present invention comprises the steps of: containing a plurality of work pieces W in a processing vessel which has a predetermined length and is capable forming a vacuum therein, oxidizing surfaces of the work pieces in an atmosphere including active oxygen species and active hydroxyl species which are generated by supplying an oxidative gas and a reductive gas into the processing vessel to interact the gases. The oxidative gas and the reductive gas are respectively supplied into the processing vessel in the longitudinal direction. Parts of the reductive gas are additionally supplied from at least two or more independently controlled gas nozzles located at separate locations in the longitudinal direction of the processing vessel. The gas flow rate through each nozzle is set depending on any combination of the work pieces composed of product wafers, dummy wafers, and monitor wafers in the processing vessel.

US Patent:

7022192, Apr 4, 2006

Filed:

Sep 4, 2002

Appl. No.:

10/233483

Inventors:

Anthony Dip - Cedar Creek TX, US
Takanori Saito - Kanagawa, JP
Raymond Joe - Austin TX, US

Assignee:

Tokyo Electron Limited - Tokyo

International Classification:

H01L 21/00
C23C 16/00

US Classification:

118725, 118728, 206832, 2194441, 219544, 392416, 392418, 15634551

Abstract:

A semiconductor wafer susceptor for batch substrate processing. The susceptor includes a central region in a primary plane and a plurality of flat annular extensions extending below the central region in a secondary plane. The primary and secondary planes are parallel to each other. An edge of the substrate overhangs the central region allowing no contact of the susceptor with the substrate edge.

US Patent:

7141765, Nov 28, 2006

Filed:

Mar 20, 2002

Appl. No.:

10/473248

Inventors:

Toshiyuki Makiya - Tachikawa, JP
Takanori Saito - Shiroyama-Machi, JP
Karuki Eickmann - Shiroyama-Machi, JP
Sanjeev Kaushal - Austin TX, US
Anthony Dip - Austin TX, US
David L. O'meara - Hopewell Junction NY, US

Assignee:

Tokyo Electron Limited - Tokyo-To

International Classification:

H05B 1/02
A21B 1/00

US Classification:

219494, 219412

Abstract:

A antireflective film is formed on a thermocouple arranged in a processing vessel of a heat treatment apparatus in order to improve the transient response characteristics of the thermocouple. In a typical embodiment, the thermocouple is made by connecting a platinum wire A and a platinum-rhodium alloy wire B, and the antireflective film is composed by stacking a silicon nitride layer C, silicon layer B and a silicon nitride layer A in that order.

US Patent:

7165011, Jan 16, 2007

Filed:

Sep 1, 2005

Appl. No.:

11/217230

Inventors:

Sanjeev Kaushal - Austin TX, US
Pradeep Pandey - San Jose CA, US
Kenji Sugishima - Tokyo, JP
Anthony Dip - Cedar Creek TX, US
David Smith - Cedar Creek TX, US
Raymond Joe - Austin TX, US
Sundar Gandhi - Austin TX, US

Assignee:

Tokyo Electron Limited - Tokyo

International Classification:

G06F 11/30
G06F 15/00

US Classification:

702182, 702183, 702185

Abstract:

A method of monitoring a thermal processing system in real-time using a built-in self test (BIST) table that includes positioning a plurality of wafers in a processing chamber in the thermal processing system; executing a real-time dynamic model to generate a predicted dynamic process response for the processing chamber during the processing time; creating a first measured dynamic process response; determining a dynamic estimation error using a difference between the predicted dynamic process response and the measured dynamic process response; and comparing the dynamic estimation error to operational thresholds established by one or more rules in the BIST table.

US Patent:

7202186, Apr 10, 2007

Filed:

Jul 31, 2003

Appl. No.:

10/630970

Inventors:

David L O'Meara - Poughkeepsie NY, US
Cory Wajda - Mesa AZ, US
Anthony Dip - Cedar Creek TX, US
Michael Toeller - Austin TX, US
Toshihara Furukawa - Essex Junction VT, US
Kristen Scheer - Milton NY, US
Alessandro Callegari - Yorktown Heights NY, US
Fred Buehrer - Poughquag NY, US
Sufi Zafar - Briarcliff Manor NY, US
Evgeni Gousev - Mahopac NY, US
Anthony Chou - Beacon NY, US
Paul Higgins - Harriman NY, US

Assignee:

Tokyo Electron Limited - Tokyo
International Business Machines Corporation (IBM) - Armonk NY

International Classification:

H01L 21/31
H01L 21/469

US Classification:

438786, 438513, 438775

Abstract:

Ultra-thin oxynitride layers are formed utilizing low-pressure processing to achieve self-limiting oxidation of substrates and provide ultra-thin oxynitride. The substrates to be processed can contain an initial dielectric layer such as an oxide layer, an oxynitride layer, or a nitride layer, or alternatively can lack an initial dielectric layer. The processing can be carried out using a batch type process chamber or a single-wafer process chamber.

US Patent:

7205187, Apr 17, 2007

Filed:

Jan 18, 2005

Appl. No.:

11/035730

Inventors:

Allen John Leith - Austin TX, US
Anthony Dip - Cedar Creek TX, US
Seungho Oh - Austin TX, US

Assignee:

Tokyo Electron Limited - Tokyo

International Classification:

H01L 21/336
H01L 21/8234

US Classification:

438197, 438637

Abstract:

A method is provided for depositing a silicon-containing film in a micro-feature on a substrate by a low pressure deposition process in a processing system. A silicon-containing film can be formed in a micro-feature by providing a substrate in a process chamber of a processing system, and exposing a hexachlorodisilane (HCD) process gas to the substrate. A processing tool containing a processing system for forming a silicon-containing film in a micro-feature using a silicon and chlorine-containing gas such as a HCD process gas is provided. Alternatively, the micro-feature can be exposed to DCS, SiCl, and SiHClgases. Alternatively, the micro-feature can be exposed to (SiH+HCl).

US Patent:

7235440, Jun 26, 2007

Filed:

Jul 31, 2003

Appl. No.:

10/630969

Inventors:

David L O'Meara - Poughkeepsie NY, US
Cory Wajda - Mesa AZ, US
Anthony Dip - Cedar Creek TX, US
Michael Toeller - Austin TX, US
Toshihara Furukawa - Essex Junction VT, US
Kristen Scheer - Milton NY, US
Alessandro Callegari - Yorktown Heights NY, US
Fred Buehrer - Poughquag NY, US
Sufi Zafar - Briarcliff Manor NY, US
Evgeni Gousev - Mahopac NY, US
Anthony Chou - Beacon NY, US
Paul Higgins - Harriman NY, US

Assignee:

Tokyo Electron Limited - Tokyo
International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/8242

US Classification:

438240, 438216, 438287, 438591

Abstract:

Ultra-thin oxide layers are formed utilizing low pressure processing to achieve self-limiting oxidation of substrates and provide ultra-thin oxide. The substrates to be processed can contain an initial dielectric layer such as an oxide layer, an oxynitride layer, a nitride layer, a high-k layer, or alternatively can lack an initial dielectric layer. The processing can be carried out using a batch type process chamber or, alternatively, using a single-wafer process chamber. One embodiment of the invention provides self-limiting oxidation of Si-substrates that results in SiOlayers with a thickness of about 15 A, where the thickness of the SiOlayers varies less than about 1 A over the substrates.