Microsoft
Hardware Verification Engineer
Qualcomm May 2012 - Aug 2018
Verification Engineer
Open-Silicon, Inc. Sep 2010 - May 2012
Senior Design and Verification Engineer
Lord Corporation Mar 2010 - Sep 2010
Fpga Engineer
Ericsson Jul 2002 - Dec 2009
Asic Design Engineer
Education:
North Carolina State University 1996 - 2001
Masters, Master of Science In Electrical Engineering, Electrical Engineering, Computer Engineering
North Carolina State University 1988 - 1993
Bachelors, Bachelor of Science In Electrical Engineering, Electrical Engineering
Skills:
Asic Verilog Vhdl Functional Verification Systemverilog Signal Integrity
Interests:
Football Casinos Collecting Antiques Exercise Nascar Home Improvement Donor Reading Gourmet Cooking Sports The Arts Golf Food Home Decoration Health Watching Sports Diy Cooking Gardening Cruises Sewing Outdoors Electronics Baseball Crafts Fitness Music Movies Collecting Kids Medicine Diet Automobiles Travel Watching Baseball Investing Traveling Tennis Watching Football
Languages:
English
Us Patents
Systems And Methods For Communicating Messages Among Cascaded Devices By Bit Shifting
Ossi I. Grohn - Apex NC Anthony S. Fugaro - Holly Springs NC
Assignee:
Ericsson Inc. - Research Triangle Park NC
International Classification:
H04J 306
US Classification:
370508, 370347, 370350, 370503
Abstract:
Messages are communicated among a plurality of devices that are serially connected, such that a preceding device is connected to a succeeding device, by receiving a message from a preceding device, bit shifting the message that was received from the preceding device and transmitting the bit shifted message that was received from the preceding device to a succeeding device. When a message is received from a succeeding device, it also is bit shifted and the bit shifted message that was received from the succeeding device is transmitted to the preceding device. Preferably, messages that are received from the preceding device are shifted in a first direction such as left by a predetermined number of bits and messages that are received from the succeeding device are shifted in a second direction that is opposite the first direction such as right by the predetermined number of bits. Preferably, the predetermined number of bits corresponds to at least one TDMA slot. Prior to shifting the message that was received from the preceding device left by the predetermined number of bits, the predetermined number of leftmost bits is extracted from the message that was received from the preceding device.
Ossi Ilari Grohn - Apex NC Anthony Salvatore Fugaro - Holly Springs NC Michael Francis Marlborough - Cary NC
Assignee:
Ericsson Inc. - Research Triangle Park NC
International Classification:
H04B 138
US Classification:
455560, 455561, 455502
Abstract:
A method and apparatus for supplying a timing signal from a central unit to at least one radio head connected to the central unit via a communications link. An external signal, typically generated by a MSC, is received at a first framer of the central unit and the first framer generates a reference clock signal based thereon. This reference clock signal is used as the transmit clock for a second framer, known as the radio head framer. The radio head framer transmits a radio head downlink signal to the radio head(s) via the communications link. The radio head downlink signal typically includes payload information and an associated timing reference signal, typically in the form of an embedded clock signal. This timing reference signal of the downlink is based on the reference clock signal from the first framer, rather than being based on a clock signal from an oscillator within the central unit. The transceivers within the radio head(s) may then control their RF transmissions using the timing reference signal from the radio head framer of the central unit.
Anthony Fugaro - Holly Springs NC, US Jeff Scott - Apex NC, US
Assignee:
Telefonaktiebolaget L M Ericsson (publ) - Stockholm
International Classification:
H04B 10/04
US Classification:
398189, 398106
Abstract:
An IR signaling generator and method divides the functionality of generation between software and hardware to provide a flexible way to generate IR signals, such as remote control signals. The hardware includes a clock generator for generating a carrier clock signal and a data clock signal, a buffer memory that is loaded with instructions representing an encoded data sequence; a control circuit, and a transmitter including a modulator. Each instruction contains an on/off value that is to be modulated with the data clock signal and a pulse duration value that indicates how long the on/off value is to modulate the clock signal. Using the data clock signal, the control circuit measures the amount of time the on/off value modulates the clock signal and causes the buffer to advance to the next instruction in the sequence when the measured amount of time is equal to the pulse duration value.
Microelectronic Packages And Packaging Methods Including Thermally And Electrically Conductive Pad
A thermally and electrically conductive (TEC) pad is disposed between a PCB and a heat sink in a cellular telephone base station. The TEC pad includes at least one aperture that overlies one or more signal vias on a ground plane of the PCB. The TEC pad apertures are larger than any underlying signal vias in order to electrically isolate the signal vias from the conductive material of the pad and the heat sink. The TEC pad allows ground vias on a PCB ground plane to ground to the heat sink.
Bus Arbitrators For Common Local Oscillators In Cellular Radiotelephone Base Stations
A transceiver board for use in a cellular radiotelephone base station comprises a first cellular radio transceiver including a first controller that controls the operation of the first transceiver, a second cellular radio transceiver including a second controller that controls the operation of the second transceiver, common local oscillator that generates a tuning signal used by the first and second transceivers for tuning a radio signal, and an arbitrator that is connected to the first and second controllers and that determines which of the first and second controllers communicates with the common local oscillator. Preferably, the arbitrator is implemented by a programmable device such as a programmable logic device (PLD) that monitors the first and second controllers to determine which controller attempts to communicate with the common local oscillator first so that that controller is allowed to communicate with a common local oscillator to the exclusion of the other controller. Alternatively, the arbitrator can be implemented by a programmable device that monitors the first and second controller and a tristate buffer that is connected to the programmable device and that connects either the first or second controller to the common local oscillator as controlled by the programmable device.