Anthony J Myers

US Patent:

6814296, Nov 9, 2004

Filed:

Apr 30, 2002

Appl. No.:

10/135308

Inventors:

Jay H. Angle - Whitehall PA
Christopher D. Gorsuch - Walnutport PA
Oscar G. Mercado - Bethlehem PA
Anthony K. Myers - Hamburg PA
John A. Schadt - Bethlehem PA
Brian W. Yeager - Schuykill Haven PA

Assignee:

Lattice Semiconductor Corp. - Hillsboro OR

International Classification:

G06K 1906

US Classification:

235492, 705 7

Abstract:

Antenna errors are corrected in an integrated circuit design utilizing spare gates distributed throughout the integrated circuit. An integrated circuit in accordance with the invention includes standard cells interspersed with spare gates. For example, the circuit may include one or more rows of spare gates arranged between groups of rows of standard cells, or islands of spare gates arranged between groups of rows of standard cells. A signal line of the integrated circuit having a detected antenna error associated therewith is coupled via one or more conductors associated with at least one metal layer of the integrated circuit to a diode or other antenna error control circuitry formed using at least one of the spare gates. The standard cells and spare gates are preferably placed in accordance with a placement operation of an automated place and route process of a standard cell computer-aided design (CAD) tool. The coupling of the signal line having the detected antenna error associated therewith to the antenna error control circuitry formed using at least one of the spare gates is preferably determined as part of a routing operation of the automated place and route process of the standard cell CAD tool.

US Patent:

6822477, Nov 23, 2004

Filed:

Jun 20, 2003

Appl. No.:

10/600042

Inventors:

Craig Bingert - Allentown PA
Christopher D. Gorsuch - Walnutport PA
Oscar G. Mercado - Bethlehem PA
Anthony K. Myers - Hamburg PA
John A. Schadt - Bethlehem PA
Brian W. Yeager - Schuykill Haven PA

Assignee:

Lattice Semiconductor Corp. - Hillsboro OR

International Classification:

H03K 19117

US Classification:

326 41, 341 38, 341 44

Abstract:

An integrated circuit includes standard cells interspersed with islands of spare gates. The spare gates are arranged in multiple groups of spare gates, with each group of spare gates within a corresponding designated spare gate area of a standard cell portion of the integrated circuit. At least a given one of the groups of spare gates is arranged between first and second rows of the standard cells and includes one or more rows of spare gates. The spare gate islands may be distributed throughout the standard cell portion of the integrated circuit in a substantially uniform manner, for example, in accordance with a predetermined geometric pattern. The spare gates may be converted to active gates in conjunction with the automated place and route process using only conductors in one or more metal layers of the integrated circuit.

US Patent:

6870395, Mar 22, 2005

Filed:

Mar 18, 2003

Appl. No.:

10/391094

Inventors:

John A. Schadt - Bethlehem PA, US
William B. Andrews - Emmaus PA, US
Zheng Chen - Macungie PA, US
Anthony K. Myers - Hamburg PA, US
David A. Rhein - Reading PA, US
Warren L. Ziegenfus - Emmaus PA, US
Fulong Zhang - Willow Grove PA, US
Ming Hui Ding - Allentown PA, US
Larry R. Fenstermaker - Nazareth PA, US

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

H01L025/00
H03K019/177
H03K017/693
G06F017/50

US Classification:

326 41, 716 14, 716 16

Abstract:

A programmable logic device (PLD) with a programmable logic core, block memory, and I/O circuitry has one or more blocks of standard-cell logic (SLBs) that are integrated into the PLD design to enable each SLB to be programmably connected to any one or more of the programmable core, the block memory, and/or the I/O circuitry. The addition of standard-cell-based functional blocks creates a PLD with increased overall logic density, a net smaller die size per function, lowered cost, and improvements to both power and performance characteristics relative to equivalent conventional PLDs, such as FPGAs.

US Patent:

6877667, Apr 12, 2005

Filed:

Aug 13, 2003

Appl. No.:

10/640804

Inventors:

Jay H. Angle - Whitehall PA, US
Christopher D. Gorsuch - Walnutport PA, US
Oscar G. Mercado - Bethlehem PA, US
Anthony K. Myers - Hamburg PA, US
John A. Schadt - Bethlehem PA, US
Brian W. Yeager - Schuykill Haven PA, US

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

G06K019/06

US Classification:

235492, 235375

Abstract:

Antenna errors are corrected in an integrated circuit design utilizing spare gates distributed throughout the integrated circuit. An integrated circuit in accordance with the invention includes standard cells interspersed with spare gates. For example, the circuit may include one or more rows of spare gates arranged between groups of rows of standard cells, or islands of spare gates arranged between groups of rows of standard cells. A signal line of the integrated circuit having a detected antenna error associated therewith is coupled via one or more conductors associated with at least one metal layer of the integrated circuit to a diode or other antenna error control circuitry formed using at least one of the spare gates. The standard cells and spare gates are preferably placed in accordance with a placement operation of an automated place and route process of a standard cell computer-aided design (CAD) tool. The coupling of the signal line having the detected antenna error associated therewith to the antenna error control circuitry formed using at least one of the spare gates is preferably determined as part of a routing operation of the automated place and route process of the standard cell CAD tool.

US Patent:

6975137, Dec 13, 2005

Filed:

Feb 10, 2005

Appl. No.:

11/055280

Inventors:

John A. Schadt - Bethlehem PA, US
William B. Andrews - Emmaus PA, US
Zheng Chen - Macungie PA, US
Anthony K. Myers - Hamburg PA, US
David A. Rhein - Reading PA, US
Warren L. Ziegenfus - Emmaus PA, US
Fulong Zhang - Willow Grove PA, US
Ming Hui Ding - Allentown PA, US
Larry R. Fenstermaker - Nazareth PA, US

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

G06F007/38
G06F017/50
H03K019/177
H03K019/00

US Classification:

326 39, 716 16

Abstract:

A programmable logic device (PLD) with a programmable logic core, block memory, and I/O circuitry has one or more blocks of standard-cell logic (SLBs) that are integrated into the PLD design to enable each SLB to be programmably connected to any one or more of the programmable core, the block memory, and/or the I/O circuitry. The addition of standard-cell-based functional blocks creates a PLD with increased overall logic density, a net smaller die size per function, lowered cost, and improvements to both power and performance characteristics relative to equivalent conventional PLDs, such as FPGAs.

US Patent:

20020163354, Nov 7, 2002

Filed:

Apr 30, 2002

Appl. No.:

10/135325

Inventors:

Craig Bingert - Allentown PA, US
Christopher Gorsuch - Walnutport PA, US
Oscar Mercado - Bethlehem PA, US
Anthony Myers - Hamburg PA, US
John Schadt - Bethlehem PA, US
Brian Yeager - Schuykill Haven PA, US

International Classification:

H03K019/003

US Classification:

326/010000

Abstract:

An integrated circuit includes standard cells interspersed with islands of spare gates. The spare gates are arranged in multiple groups of spare gates, with each group of spare gates within a corresponding designated spare gate area of a standard cell portion of the integrated circuit. At least a given one of the groups of spare gates is arranged between first and second rows of the standard cells and includes one or more rows of spare gates, with each row of spare gates including multiple base transistor structures arranged adjacent to one another along longitudinal dimensions of the structures. The standard cells and spare gates are preferably placed in accordance with a placement operation of an automated place and route process of a standard cell computer-aided design (CAD) tool. The spare gates may be implemented using a base transistor structure compatible with the standard cell CAD tool. The spare gate islands may be distributed throughout the standard cell portion of the integrated circuit in a substantially uniform manner, for example, in accordance with a predetermined geometric pattern. The spare gates may be converted to active gates in conjunction with the automated place and route process using only conductors in one or more metal layers of the integrated circuit.