Anthony Ngia Nguyen

US Patent:

7350036, Mar 25, 2008

Filed:

Aug 1, 2005

Appl. No.:

11/195224

Inventors:

Daehyun Kim - San Jose CA, US
Victor W. Lee - San Jose CA, US
Anthony D. Nguyen - Mountain View CA, US
Mikhail Smelyanskiy - Mountain View CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/14

US Classification:

711149

Abstract:

A technique to perform concurrent updates to a shared data structure. At least one embodiment of the invention concurrently stores copies of a data structure within a plurality of local caches, updates the local caches with a partial result of a computation distributed among a plurality of processing elements, and returns the partial results to combining logic in parallel, which combines the partial results into a final result.

US Patent:

7856537, Dec 21, 2010

Filed:

Sep 30, 2004

Appl. No.:

10/956179

Inventors:

Sanjeev Kumar - San Jose CA, US
Christopher J. Hughes - San Jose CA, US
Partha Kundu - Palo Alto CA, US
Anthony Nguyen - Mountain View CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/00
G06F 13/28
G06F 12/00

US Classification:

711152, 711147, 711E12094, 710200

Abstract:

Embodiments of the invention relate a hybrid hardware and software implementation of transactional memory accesses in a computer system. A processor including a transactional cache and a regular cache is utilized in a computer system that includes a policy manager to select one of a first mode (a hardware mode) or a second mode (a software mode) to implement transactional memory accesses. In the hardware mode the transactional cache is utilized to perform read and write memory operations and in the software mode the regular cache is utilized to perform read and write memory operations.

US Patent:

8457153, Jun 4, 2013

Filed:

Apr 4, 2011

Appl. No.:

13/079761

Inventors:

Anthony Nguyen - San Jose CA, US
David Lai - Mountain View CA, US
Norman Tang - Los Altos CA, US
Nick Peng - Santa Clara CA, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

H04J 3/22

US Classification:

370466, 370465, 370463, 370464, 370546, 370474

Abstract:

The practical transmission range of an electrical cable can be extended by converting between electrical and optical signals using an HDMI-optical converter that receives an SFP+ optics transceiver. A pair of SFP+-based HDMI adapters/extenders can connect to a pair of HDMI cables, where one of the HDMI cables is connected to an HDMI Source and one of the HDMI cables is connected to an HDMI Sink. Each of the SFP+-based HDMI cable extenders can terminate with an SFP+ port to house a hot pluggable SFP+ transceiver. The apparatus can transmit 10 G video data to the distance that is supported by the SFP+ product.

US Patent:

20070150663, Jun 28, 2007

Filed:

Dec 27, 2005

Appl. No.:

11/316949

Inventors:

Abraham Mendelson - Haifa, IL
Julius Mandelblat - Haifa, IL
Christopher Hughes - San Jose CA, US
Daehyun Kim - San Jose CA, US
Victor Lee - San Jose CA, US
Anthony Nguyen - Mountain View CA, US
Yen-Kuang Chen - Cupertino CA, US

International Classification:

G06F 13/00

US Classification:

711141000

Abstract:

Some embodiments of the invention provide devices, systems and methods of cache coherence. For example, an apparatus in accordance with an embodiment of the invention includes a memory to store a memory line; and a cache controller logic to assign a first cache coherence state to the memory line in relation to a first component, and to assign a second, different, cache coherence state to the memory line in relation to a second, different, component.

US Patent:

20070226735, Sep 27, 2007

Filed:

Mar 22, 2006

Appl. No.:

11/386443

Inventors:

Anthony Nguyen - Castro Valley CA, US
Engin Ipek - Ithaca NY, US
Victor Lee - San Jose CA, US
Daehyun Kim - San Jose CA, US
Mikhail Smelyanskiy - Mountain View CA, US

International Classification:

G06F 9/455

US Classification:

718 1

Abstract:

Methods and apparatus to provide virtualized vector processing are described. In one embodiment, one or more operations corresponding to a virtual vector request are distributed to one or more processor cores for execution.

US Patent:

20090038623, Feb 12, 2009

Filed:

Aug 15, 2008

Appl. No.:

12/192924

Inventors:

John Michael Farbarik - Castro Valley CA, US
Anthony Nguyen - Milpitas CA, US
Anant V. Hegde - Hayward CA, US
Casidy Domingo - San Mateo CA, US
Charisse Yung - Los Altos Hills CA, US
Nikhil D. Bhat - Fremont CA, US
George Yoseung Choi - Redwood City CA, US

Assignee:

Pavad Medical, Inc. - Fremont CA

International Classification:

A61F 5/56
H02J 7/00

US Classification:

128848, 320108

Abstract:

An inductive power transfer system associated with an airway implant device is disclosed. A non-implanted portion of the system comprises a mouthpiece or retainer. The mouthpiece includes a power transfer circuit and a power source. The power transfer circuit includes a receive circuit configured to receive a first inductive power transfer from a charging device and to deliver a charging current to the power source. The power transfer circuit also includes a transmit circuit coupled to the power source. The transmit circuit is configured to provide a second inductive power transfer from the mouthpiece to the airway implant. Some embodiments of the non-implanted portion include a charge controller and a lithium polymer battery. Some embodiments of the charging device include a microcontroller for controlling operation of the charging device based on a proximity of the mouthpiece.

US Patent:

20100073368, Mar 25, 2010

Filed:

Sep 22, 2008

Appl. No.:

12/234988

Inventors:

Changkyu Kim - San Jose CA, US
Jatin Chhugani - Santa Clara CA, US
Christian Bienia - Princeton NJ, US
Daehyun Kim - San Jose CA, US
Anthony Nguyen - Castro Valley CA, US
Sanjeev Kumar - San Jose CA, US

International Classification:

G06T 15/40
G06T 15/00

US Classification:

345422, 345419

Abstract:

Methods and systems to determine view cell occlusion, including to project objects of a 3-dimensional graphics environment to a 2-dimensional image plane with respect to the view point, to reduce sizes of corresponding object images, to generate an occluder map from the reduced-size object images, to compare at least a portion of the object images to the occluder map, and to identify an object as occluded with respect to the view cell when pixel depth values of the object image are greater than corresponding pixel depth values of the occluder map. Methods and systems to reduce an object image size include methods and systems to nullify pixel depth values within a radius of an edge pixel, and to determine the radius as a distance from the edge pixel to a second pixel so that a line between the view point and the second pixel is parallel with one or more of a line and a plane that is tangential to a sphere enclosing the view cell and a point on the object that corresponds to the edge pixel.

US Patent:

20110055837, Mar 3, 2011

Filed:

Nov 10, 2010

Appl. No.:

12/943848

Inventors:

Sanjeev Kumar - San Jose CA, US
Christopher J. Hughes - San Jose CA, US
Partha Kundu - Palo Alto CA, US
Anthony Nguyen - Mountain View CA, US

International Classification:

G06F 9/46

US Classification:

718101

Abstract:

Embodiments of the invention relate a hybrid hardware and software implementation of transactional memory accesses in a computer system. A processor including a transactional cache and a regular cache is utilized in a computer system that includes a policy manager to select one of a first mode (a hardware mode) or a second mode (a software mode) to implement transactional memory accesses. In the hardware mode the transactional cache is utilized to perform read and write memory operations and in the software mode the regular cache is utilized to perform read and write memory operations.