Antonio Gallerano from 3906 Ross Ave, San Jose, CA 95124, Phone: 4082646038

Resumes

Principal Device Engineer

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Location:

3906 Ross Ave, San Jose, CA 95124

Industry:

Semiconductors

Work:

Texas Instruments since Feb 2010
Principal Device Engineer
ALTERA Jun 2005 - Feb 2010
Device Engineer, Member of Technical Staff
Alliance Semiconductor Oct 2003 - May 2005
Sr. Device Engineer
PDF Solutions 2001 - 2003
Device Engineer
STMicroelectronics 1998 - 2001
Process Development Engineer

Education:

University of Pisa Oct 1991 - Apr 1998
Liceo Scientifico 1991 - 1991

Skills:

Mixed Signal
Cmos
Semiconductors
Ic
Silicon
Asic
Power Management
Analog
Soc
Simulations

Us Patents

Cdm Performance Of High Speed Clk Inputs
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US Patent:

7760477, Jul 20, 2010
Filed:

Oct 8, 2007
Appl. No.:

11/868705
Inventors:

Jeffrey T. Watt - Palo Alto CA, US
Antonio Gallerano - San Jose CA, US
Assignee:

Altera Corporation - San Jose CA
International Classification:

H02H 9/00
H02H 1/00
US Classification:

361 56
Abstract:

A conventional ESD protection circuit connects a diode and main clamp between a pad or node to be protected and ground. To preserve high speed operation while improving charge device model (CDM) performance, the invention also connects between pad and ground a small diode in series with a secondary clamp and a small isolation resistance. The isolation resistance is approximately 20 ohms. The secondary clamp can be as small as 30 nm wide. Parallel diodes on the main clamp can be replaced with an N+/p-substrate (native) diode to further reduce capacitance.

I/O Esd Protection Device For High Performance Circuits
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US Patent:

7808047, Oct 5, 2010
Filed:

Aug 31, 2007
Appl. No.:

11/897915
Inventors:

Antonio Gallerano - San Jose CA, US
Cheng-Hsiung Huang - Cupertino CA, US
Chih-Ching Shih - Pleasanton CA, US
Jeffrey T. Watt - Palo Alto CA, US
Assignee:

Altera Corporation - San Jose CA
International Classification:

H01L 23/62
US Classification:

257355, 257356, 257360, 361111
Abstract:

A trigger circuit is provided for a pull-down device by connecting a diode between the I/O pad and the body of the pull-down device. In one embodiment, the pull-down device is formed as a plurality of discrete transistors in a single well. The drain of each transistor is connected through a ballast resistor to the I/O pad; and the source of each transistor is connected through a ballast resistor to ground. The trigger circuit is a diode formed in a different well from that of the transistors. The cathode of the diode is connected to the I/O pad and the anode is connected to the transistor well through a center tap located between the transistors. Preferably, the transistors are NMOS transistors formed in a P-well. Advantageously, the diode is an N+/PLDD diode. Alternatively, the diode is an N+/P diode where the P region is formed by an ESD implant.

Esd Protection Structure
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US Patent:

7859804, Dec 28, 2010
Filed:

Aug 9, 2007
Appl. No.:

11/836705
Inventors:

Antonio Gallerano - Redwood City CA, US
Jeffrey T. Watt - Palo Alto CA, US
Assignee:

Altera Corporation - San Jose CA
International Classification:

H02H 9/00
US Classification:

361 56
Abstract:

This relates to a sense circuit to detect an ESD event and turn on an SCR to discharge the ESD event. In a preferred embodiment, the circuit comprises a resistor in the signal path to/from an I/O buffer, a sense circuit in parallel with the resistor, an SCR connected between ground and a node between the resistor and the I/O pad, and an I/O buffer connected between ground and the other end of the resistor. When the sense circuit detects a significant voltage drop across the resistor, it injects current into the SCR, thereby turning on the SCR and discharging the ESD event.

Low Capacitance Esd Protection Structure For High Speed Input Pins
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US Patent:

7885046, Feb 8, 2011
Filed:

Oct 10, 2007
Appl. No.:

11/869805
Inventors:

Antonio Gallerano - San Jose CA, US
Cheng-Hsiung Huang - Cupertino CA, US
Jeffrey T. Watt - Palo Alto CA, US
Assignee:

Altera Corporation - San Jose CA
International Classification:

H02H 9/00
H02H 1/00
US Classification:

361 56
Abstract:

A conventional ESD protection circuit comprises an SCR and a first diode connected in series between ground and a node or pad to be protected and a second diode connected between ground and the node to be protected. An anode of the first diode and a cathode of the second diode are connected to the node to be protected. In one embodiment of the invention, the capacitance of the second diode is reduced by forming the second diode from a PN junction between a heavily doped region of one conductivity type and a substrate region instead of a well region of the opposite conductivity type. The reduction in the capacitance of the second diode makes it possible to increase the size of the first diode and SCR, thereby decreasing their resistance, while keeping the total capacitance of the ESD circuit at or below the capacitance of the prior art ESD circuit. A second embodiment of an ESD protection comprises an SCR and a first diode connected in series between ground and node to be protected and second and third diodes connected in series between ground and the node to be protected with the anode of the second diode connected to ground. Again, the capacitance of the second diode is reduced by forming the diode from a PN junction between a heavily doped region of one conductivity type and a substrate region of the other conductivity type.

I/O Esd Protection Device For High Performance Circuits
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US Patent:

7955923, Jun 7, 2011
Filed:

Jul 28, 2010
Appl. No.:

12/845337
Inventors:

Antonio Gallerano - San Jose CA, US
Cheng-Hsiung Huang - Cupertino CA, US
Chih-Ching Shih - Pleasanton CA, US
Jeffrey T. Watt - Palo Alto CA, US
Assignee:

Altera Corporation - San Jose CA
International Classification:

H01L 21/8238
US Classification:

438217
Abstract:

A trigger circuit is provided for a pull-down device by connecting a diode between the I/O pad and the body of the pull-down device. In one embodiment, the pull-down device is formed as a plurality of discrete transistors in a single well. The drain of each transistor is connected through a ballast resistor to the I/O pad; and the source of each transistor is connected through a ballast resistor to ground. The trigger circuit is a diode formed in a different well from that of the transistors. The cathode of the diode is connected to the I/O pad and the anode is connected to the transistor well through a center tap located between the transistors. Preferably, the transistors are NMOS transistors formed in a P-well. Advantageously, the diode is an N+/PLDD diode. Alternatively, the diode is an N+/P diode where the P region is formed by an ESD implant.

Electrostatic Discharge Protection In A Field Programmable Gate Array
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US Patent:

7990664, Aug 2, 2011
Filed:

Dec 14, 2006
Appl. No.:

11/639792
Inventors:

Srinivas Perisetty - Santa Clara CA, US
Antonio Gallerano - Redwood City CA, US
Jeffrey T. Watt - Palo Alto CA, US
Cheng-Hsiung Huang - Cupertino CA, US
Assignee:

Altera Corporation - San Jose CA
International Classification:

H02H 9/00
H02H 3/22
US Classification:

361 56, 361111
Abstract:

An ESD protection circuit is integrated into the core of an FPGA in a distributed fashion coupling the bodies of one or more transistors to the power supply pin and/or the ground pin of the FPGA. The ESD protection circuit includes one or more positive discharge paths and one or more negative discharge paths. In the case of a positive ESD event, the positive discharge paths are on and the negative discharge paths are off. In the case of a negative ESD event, the positive discharge paths are off and the negative discharge paths are on. In either event, the bodies of the transistors track the voltages at the power supply pin and/or the ground pin to protect the core from being by damaged by electrostatic discharge.

Esd Protection For Differential Output Pairs
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US Patent:

8116048, Feb 14, 2012
Filed:

Oct 12, 2009
Appl. No.:

12/577547
Inventors:

Antonio Gallerano - San Jose CA, US
Charles Y. Chu - Cupertino CA, US
Jeffrey T. Watt - Palo Alto CA, US
Assignee:

Altera Corporation - San Jose CA
International Classification:

H02H 3/22
US Classification:

361 56, 361111
Abstract:

In a conventional differential output circuit, the output terminals are connected to the drains of a differential pair of transistors and the sources of the transistors are connected together at a first node. The bodies of the transistors are connected to a second node having a potential different from that of the first node. In the event of a HBM ESD event, discharge may take place through the differential transistors, leading to destruction of one of them. To reduce the likelihood of such discharge, in a preferred embodiment, switches are provided to connect the body of each of the differential transistors to the first node when an ESD event is sensed. In an alternative embodiment, a switch is provided to connect the first node to the second node when an ESD event is sensed.

Method And Apparatus For Improving Triggering Uniformity Of Snapback Electrostatic Discharge Protection Devices
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US Patent:

8120112, Feb 21, 2012
Filed:

Sep 28, 2007
Appl. No.:

11/904706
Inventors:

Jeffrey T. Watt - Palo Alto CA, US
Antonio Gallerano - San Jose CA, US
Assignee:

Altera Corporation - San Jose CA
International Classification:

H01L 23/58
US Classification:

257355, 257 65, 257141, 257213
Abstract:

An electrostatic discharge (ESD) protection circuit includes a first array of transistors, having source and drain doped with a first type of material, arranged in parallel in a first block, and a second array of transistors, having source and drain doped with the first type of material, arranged in parallel in a second block. The ESD protection circuit also includes an active region between the first and second array of transistors doped with a second type of material that is complementary to the first type of material.