Anurag Te Gupta

US Patent:

6405286, Jun 11, 2002

Filed:

Jul 19, 2001

Appl. No.:

09/910272

Inventors:

Anurag Gupta - Santa Clara CA
Amil Kabil - Sunnyvale CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1200

US Classification:

711127, 711157, 711168, 711 5

Abstract:

A method and apparatus determines interleaving schemes in a computer system that supports multiple interleaving schemes. In one embodiment, a memory interleaving scheme lookup table is used to assign memory interleaving schemes based on the number of available bank bits. In another embodiment, the percentage of concurrent memory operations is increased by assigning memory interleaving schemes to bank bits based on the classification of bank bits. The present invention supports a memory organization that provides separate memory busses that support independent simultaneous memory transactions, and memory bus segments that allow memory read operations to be overlapped with memory write operations, with each memory bus segment capable of carrying single memory operation at any given time. Bank bits that distinguish between memory busses are classified as class A, bank bits that distinguish between memory bus segments are classified as class B, and bank bits that distinguish between banks on a single memory bus segment are classified as class C. The memory controller supports multi-cache line interleaving (MCI), cache effect interleaving (CEI), and DRAM page interleaving (DPI).

US Patent:

6636952, Oct 21, 2003

Filed:

Jun 15, 2001

Appl. No.:

09/880873

Inventors:

Song Zhang - San Jose CA
Anurag P. Gupta - Saratoga CA
Raymond Lim - Mountain View CA
Jorge Cruz-Rios - Los Altos CA
Phil Lacroute - Sunnyvale CA

Assignee:

Juniper Networks, Inc. - Sunnyvale CA

International Classification:

G06F 1300

US Classification:

711154, 711137

Abstract:

A network device includes systems and methods for processes streams of data. The network device stores data and addresses corresponding to the streams in a memory. The addresses store pointers to the data. Output logic within the network device determines whether an address is required to be fetched. When no address is required to be fetched, then data is read from the memory. When an address is required to be fetched, the address is fetched from the memory and data is read from the memory using the fetched address. To facilitate this, notifications may be stored corresponding to the streams and notification pointers may be used to identify ones of the notifications to be processed. A prefetch pointer may also be used to identify a notification with one or more associated addresses to be prefetched.

US Patent:

6807594, Oct 19, 2004

Filed:

Jul 16, 2001

Appl. No.:

09/905071

Inventors:

Pradeep Sindhu - Los Altos Hill CA
Song Zhang - San Jose CA
Anurag P. Gupta - Saratoga CA
Phil Lacroute - Sunnyvale CA

Assignee:

Juniper Networks, Inc. - Sunnyvale CA

International Classification:

G06F 1314

US Classification:

710240, 37039531

Abstract:

A system having multiple arbiters is constructed to reduce the chances of arbiters synchronizing with one another. Each arbiter includes a random process that introduces randomness into an arbitration scheme performed by the arbiter. Because of the randomness, the arbiters will not tend to synchronize with one another, even when receiving an identical stream of input values.

US Patent:

6964484, Nov 15, 2005

Filed:

Feb 2, 2004

Appl. No.:

10/770069

Inventors:

Anurag Gupta - Corvallis OR, US
Peter Guy Howard - Junction City OR, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G03B021/14
G03B021/28
G02B026/08

US Classification:

353 69, 353 81, 359207

Abstract:

A technique is described to reduce overfill of light that has exited a light integrating device and is applied to an optical modulator in the form of an illuminating pattern. The illumination reduction technique makes the illuminating pattern more closely conform to a active planar surface of the optical modulator by at least partially providing anamorphic magnification of the illuminating pattern.

US Patent:

7046419, May 16, 2006

Filed:

Aug 13, 2004

Appl. No.:

10/917653

Inventors:

Anurag Gupta - Corvallis OR, US
Peter Guy Howard - Junction City OR, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G02B 26/00

US Classification:

359290, 359298

Abstract:

A digital micromirror device arrangement and devices using the arrangement are disclosed. The arrangement includes a digital micromirror device (DMD) having an active area, a cover plate disposed substantially adjacent to the DMD and having a thickness and a light blocking area having an aperture formed therein. The active area is adapted to receive incoming light and to reflect the incoming light as outgoing light. The light-blocking layer is offset from a plane of the active area by at least the thickness of the cover plate and is adapted to block light from passing therethrough. The aperture is dimensioned to produce a beam of outgoing light having desired dimensions.

US Patent:

7052142, May 30, 2006

Filed:

Apr 30, 2004

Appl. No.:

10/836920

Inventors:

Anurag Gupta - Corvallis OR, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G03B 21/00
G03B 21/28

US Classification:

353 46, 353 51, 353 99

Abstract:

A light projecting device including an image resolution enhancing mechanism that spatially offsets at least one pixel between an original pixel position and an offset pixel position. The image resolution enhancing mechanism includes a dual mirror mechanism to provide the spatial offset.

US Patent:

7054069, May 30, 2006

Filed:

Jan 31, 2005

Appl. No.:

11/048569

Inventors:

Anurag Gupta - Corvallis OR, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G02B 3/00
G02B 15/14

US Classification:

359649, 359680, 359676

Abstract:

A projection lens system is comprised of five lens groups. A first lens group forms a negative power lens group, and a second lens group forms a positive power lens group. Third, fourth, and fifth lens groups, when combined, form a positive power lens group, which helps to compensate for aberrations. At least one of the component lenses moves to adjust the system's focus. An image display system that includes such a projection lens system can project digital optical images for projection and other image display applications.

US Patent:

7101063, Sep 5, 2006

Filed:

Feb 5, 2004

Appl. No.:

10/772999

Inventors:

Michael Long - Corvallis OR, US
P. Guy Howard - Junction City OR, US
Anurag Gupta - Corvallis OR, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

F21V 5/00

US Classification:

362328, 362235, 362339, 362608, 362624

Abstract:

A light integrating system includes at least one total internal reflection (TIR) prism and a light integrating device disposed to collect and homogenize light exiting from the TIR prism.