Anurag Te Gupta

US Patent:

6405286, Jun 11, 2002

Filed:

Jul 19, 2001

Appl. No.:

09/910272

Inventors:

Anurag Gupta - Santa Clara CA
Amil Kabil - Sunnyvale CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1200

US Classification:

711127, 711157, 711168, 711 5

Abstract:

A method and apparatus determines interleaving schemes in a computer system that supports multiple interleaving schemes. In one embodiment, a memory interleaving scheme lookup table is used to assign memory interleaving schemes based on the number of available bank bits. In another embodiment, the percentage of concurrent memory operations is increased by assigning memory interleaving schemes to bank bits based on the classification of bank bits. The present invention supports a memory organization that provides separate memory busses that support independent simultaneous memory transactions, and memory bus segments that allow memory read operations to be overlapped with memory write operations, with each memory bus segment capable of carrying single memory operation at any given time. Bank bits that distinguish between memory busses are classified as class A, bank bits that distinguish between memory bus segments are classified as class B, and bank bits that distinguish between banks on a single memory bus segment are classified as class C. The memory controller supports multi-cache line interleaving (MCI), cache effect interleaving (CEI), and DRAM page interleaving (DPI).

US Patent:

6636952, Oct 21, 2003

Filed:

Jun 15, 2001

Appl. No.:

09/880873

Inventors:

Song Zhang - San Jose CA
Anurag P. Gupta - Saratoga CA
Raymond Lim - Mountain View CA
Jorge Cruz-Rios - Los Altos CA
Phil Lacroute - Sunnyvale CA

Assignee:

Juniper Networks, Inc. - Sunnyvale CA

International Classification:

G06F 1300

US Classification:

711154, 711137

Abstract:

A network device includes systems and methods for processes streams of data. The network device stores data and addresses corresponding to the streams in a memory. The addresses store pointers to the data. Output logic within the network device determines whether an address is required to be fetched. When no address is required to be fetched, then data is read from the memory. When an address is required to be fetched, the address is fetched from the memory and data is read from the memory using the fetched address. To facilitate this, notifications may be stored corresponding to the streams and notification pointers may be used to identify ones of the notifications to be processed. A prefetch pointer may also be used to identify a notification with one or more associated addresses to be prefetched.

US Patent:

6807594, Oct 19, 2004

Filed:

Jul 16, 2001

Appl. No.:

09/905071

Inventors:

Pradeep Sindhu - Los Altos Hill CA
Song Zhang - San Jose CA
Anurag P. Gupta - Saratoga CA
Phil Lacroute - Sunnyvale CA

Assignee:

Juniper Networks, Inc. - Sunnyvale CA

International Classification:

G06F 1314

US Classification:

710240, 37039531

Abstract:

A system having multiple arbiters is constructed to reduce the chances of arbiters synchronizing with one another. Each arbiter includes a random process that introduces randomness into an arbitration scheme performed by the arbiter. Because of the randomness, the arbiters will not tend to synchronize with one another, even when receiving an identical stream of input values.

US Patent:

7106696, Sep 12, 2006

Filed:

Aug 31, 2001

Appl. No.:

09/942630

Inventors:

Raymond Marcelino Manese Lim - Los Altos Hills CA, US
Song Zhang - San Jose CA, US
Anurag P. Gupta - Saratoga CA, US
Brian Gaudet - San Jose CA, US

Assignee:

Juniper Networks, Inc. - Sunnyvale CA

International Classification:

G06F 11/00
H04L 12/26

US Classification:

3702301, 370232, 370235, 370253

Abstract:

A system controls the transfer of data. The system receives a request to transfer data and determines whether a counter value equals or exceeds a threshold. The counter value represents an amount of time since a previous data transfer. When the counter value equals or exceeds the threshold, the system transmits the data. In another implementation, the system tracks the amount of data read from a buffer. The system reduces the speed at which data is read when the amount of data read from the buffer exceeds a threshold.

US Patent:

7110360, Sep 19, 2006

Filed:

Nov 5, 2001

Appl. No.:

09/985683

Inventors:

Lawrence Hui - Sunnyvale CA, US
Song Zhang - San Jose CA, US
Anurag P. Gupta - Saratoga CA, US
Phil Lacroute - Sunnyvale CA, US
Michael Beesley - Hillsborough CA, US

Assignee:

Juniper Networks, Inc. - Sunnyvale CA

International Classification:

H04L 12/26

US Classification:

370235, 370252

Abstract:

A fabric request controller implements flow control for data cells to a network or switch fabric. The fabric request controller issues request messages to the fabric switch and receives back corresponding grant messages. The fabric request controller includes a credit counter for metering the number of allowable outstanding requests. A fake request vector component periodically issues fake requests to compensate for information loss on the switch fabric.

US Patent:

7120113, Oct 10, 2006

Filed:

Jul 16, 2001

Appl. No.:

09/905068

Inventors:

Song Zhang - San Jose CA, US
Jorge Cruz-Rios - Los Altos CA, US
Anurag P. Gupta - Saratoga CA, US

Assignee:

Juniper Networks, Inc. - Sunnyvale CA

International Classification:

G08C 15/00
H04J 3/14
H04L 1/00
H04L 12/26
H04L 12/28
H04L 12/56

US Classification:

370229, 370412

Abstract:

A method for processing high priority packets and low priority packets in a network device includes performing arbitration on high priority packets until no high priority packets remain. Arbitration then is enabled on low priority packets. A packet size associated with the selected low priority packet is compared with a programmable threshold. Low priority packets are excluded from subsequent arbitration for a programmable duration when the packet size exceeds the programmable threshold.

US Patent:

7187689, Mar 6, 2007

Filed:

Oct 29, 2001

Appl. No.:

09/984315

Inventors:

Anurag P Gupta - Saratoga CA, US
Song Zhang - San Jose CA, US

Assignee:

Juniper Networks, Inc. - Sunnyvale CA

International Classification:

H04L 12/54

US Classification:

370429, 711159

Abstract:

A system manages a buffer having a group of entries. The system receives information relating to a read request for a memory. The system determines whether an entry in the buffer contains valid information. If the entry is determined to contain valid information, the system transmits the information in the entry in an error message. The system may then store the received information in the entry. In another implementation, the system stores data in one of the entries of the buffer, removes an address corresponding to the one entry from an address list, and starts a timer associated with the one entry. The system also determines whether the timer has exceeded a predetermined value, transferring the data from the one entry when the timer has exceeded the predetermined value, and adds the address back to the address list.

US Patent:

7346001, Mar 18, 2008

Filed:

Sep 5, 2006

Appl. No.:

11/470057

Inventors:

Song Zhang - San Jose CA, US
Jorge Cruz-Rios - Los Altos CA, US
Anurag P. Gupta - Saratoga CA, US

Assignee:

Juniper Networks, Inc. - Sunnyvale CA

International Classification:

G06F 11/00
H04J 3/14
H04L 12/26
H04L 12/28
H04L 12/56
H04L 12/54

US Classification:

370235, 370412, 370428

Abstract:

A method for processing high priority packets and low priority packets in a network device includes performing arbitration on high priority packets until no high priority packets remain. Arbitration then is enabled on low priority packets. A packet size associated with the selected low priority packet is compared with a programmable threshold. Low priority packets are excluded from subsequent arbitration for a programmable duration when the packet size exceeds the programmable threshold.