Anuwat C Saetow

US Patent:

20130179724, Jul 11, 2013

Filed:

Jan 5, 2012

Appl. No.:

13/343938

Inventors:

Edgar R. Cordero - Round Rock TX, US
Joab D. Henderson - Austin TX, US
Divya Kumar - Austin TX, US
Jeffrey A. Sabrowski - Leander TX, US
Anuwat Saetow - Austin TX, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 11/20

US Classification:

714 63, 714E11089

Abstract:

A method, system and computer program product are provided for implementing hardware assisted Dynamic Random Access Memory (DRAM) repair in a computer system that supports ECC. A data register providing DRAM repair is selectively provided in one of the Dynamic Random Access Memory (DRAM), a memory controller, or a memory buffer coupled between the DRAM and the memory controller. The data register is configured to map to any address. Responsive to the configured address being detected, the reads to or the writes from the configured address are routed to the data register.

US Patent:

20130262791, Oct 3, 2013

Filed:

Mar 27, 2012

Appl. No.:

13/430807

Inventors:

Joab D. Henderson - Pflugerville TX, US
Ryan J. Pennington - Austin TX, US
Anuwat Saetow - Austin TX, US
Robert B. Tremaine - Stormville NY, US
Kenneth L. Wright - Austin TX, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 12/00

US Classification:

711154, 711E12001

Abstract:

An embodiment is a method for operating a memory system, the method including storing initial calibration values for each of a first frequency and second frequency for a memory device, performing a periodic calibration to determine a calibration update value for operation of the memory device at the first frequency, combining the calibration update value with the initial calibration value for the first frequency to provide an updated calibration for operation of the memory device at an operating frequency of the first frequency and receiving a frequency change request at a memory controller associated with the memory device. The method further includes blocking traffic to the memory device, adjusting operating frequency to the second frequency while the memory device remains powered, combining the calibration update value with the initial calibration value for the second frequency for operation at the second frequency and enabling traffic to the memory device.

US Patent:

20130262792, Oct 3, 2013

Filed:

Mar 27, 2012

Appl. No.:

13/431108

Inventors:

Joab D. Henderson - Pflugerville TX, US
Ryan J. Pennington - Austin TX, US
Anuwat Saetow - Austin TX, US
Robert B. Tremaine - Stormville NY, US
Kenneth L. Wright - Austin TX, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 12/00

US Classification:

711154, 711E12001

Abstract:

An embodiment is a method includes writing a first set of memory device parameters to a first mode register in a memory device, wherein the first set of memory device parameters correspond to a first frequency, monitoring selected parameters for the memory system while the memory device operates at the first frequency and predicting a second frequency that the memory device will operate at subsequent to the first frequency, the predicting being based on the monitored selected parameters. The method further includes writing a second set of memory device parameters to second mode register in the memory device, receiving a frequency change request at a memory controller associated with the memory device, the frequency change request to operate at a new frequency and updating the first mode register with the second set of memory device parameters from the second mode register responsive to the new frequency being equal to the second frequency.

US Patent:

20140068322, Mar 6, 2014

Filed:

Aug 29, 2012

Appl. No.:

13/598072

Inventors:

Edgar R. Cordero - Round Rock TX, US
Joab D. Henderson - Pflugerville TX, US
Divya Kumar - Austin TX, US
Jeffrey A. Sabrowski - Leander TX, US
Anuwat Saetow - Austin TX, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 11/14

US Classification:

714 611, 714E11113

Abstract:

A method, system and computer program product are provided for implementing command timing adjustments to alleviate Dynamic Random Access Memory (DRAM) failures in a computer system. A predefined DRAM failure is detected. Responsive to the detected failure, a set of timers is adjusted for controlling predetermined timings used to access the DRAM. Responsive to the failure being resolved by the adjusted set of timers, checking for a predetermined level of performance is performed.

US Patent:

20130038380, Feb 14, 2013

Filed:

Aug 11, 2011

Appl. No.:

13/207688

Inventors:

Edgar R. Cordero - Round Rock TX, US
Divya Kumar - Austin TX, US
Anuwat Saetow - Austin TX, US
Robert B. Tremaine - Stormville NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H03H 11/00
G06F 17/50
H01L 29/68

US Classification:

327524, 257 48, 716100, 257E29169

Abstract:

A method and circuit for implementing a chip to chip calibration in a chip stack, for example, with through silicon vias (TSV) stack, and a design structure on which the subject circuit resides are provided. A first chip and a second chip are included within a semiconductor chip stack. The semiconductor chip stack includes a vertical stack optionally provided with Though Silicon Via (TSV) stacking of the chips. At least one of the first chip and the second chip includes a calibration control circuit and a performance indicator circuit coupled to the calibration control circuit to train and calibrate at least one of the first chip and the second chip to provide enhanced performance and reliability for the semiconductor chip stack.

US Patent:

20200264936, Aug 20, 2020

Filed:

Feb 14, 2019

Appl. No.:

16/275716

Inventors:

- Armonk NY, US
Saravanan Sethuraman - Bangalore, IN
Edgar R. Cordero - Round Rock TX, US
Anuwat Saetow - Austin TX, US
Diyanesh B. Chinnakkonda Vidyapoornachary - Bangalore, IN

International Classification:

G06F 9/50
G06F 9/38
G06F 13/16

Abstract:

A method for configuring hardware within a computing system. The method includes one or more computer processors identifying information respectively associated with a plurality of hardware resources within a portion of a computing system. The method further includes determining whether a set of memory modules of differing performance ratings are operatively coupled to a shared bus fabric. The method further includes responding to determining that the set of memory modules of differing performance ratings is operatively coupled to the shared bus fabric by configuring a subsystem to selectively access respective groups of memory modules within the set of memory modules based on a performance rating corresponding to a respective group of memory modules.

US Patent:

20200192739, Jun 18, 2020

Filed:

Dec 13, 2018

Appl. No.:

16/219252

Inventors:

- Armonk NY, US
William V. Huott - Holmes NY, US
Anuwat Saetow - Austin TX, US
Adam J. McPadden - Underhill VT, US

International Classification:

G06F 11/07

Abstract:

A method and a circuit for implementing single event upset (SEU) parity detection, and a design structure on which the subject circuit resides are provided. The circuit implements detection of unwanted state changes due to SEUs, noise or other event in a latch having a default state of zero. The latch includes an L1 latch and an L2 latch with the L2 latch having the connected output and is used and monitored for a flip. A pair of series-connected field effect transistors (FETs) is connected between a drive input of a parity control circuit and ground potential. An inverted output of the L1 latch and a true output of the L2 latch is applied to a respective gate of the pair of series-connected FETs.

US Patent:

20200192751, Jun 18, 2020

Filed:

Dec 13, 2018

Appl. No.:

16/219166

Inventors:

- Armonk NY, US
Adam J. McPadden - Underhill VT, US
Anuwat Saetow - Austin TX, US
David D. Cadigan - Fairfield NY, US

International Classification:

G06F 11/10
H03K 3/037

Abstract:

A method and a circuit for implementing dynamic single event upset (SEU) detection and correction, and a design structure on which the subject circuit resides are provided. The circuit implements detection, correction and scrubbing of unwanted state changes due to SEUs, noise or other event in semiconductor circuits. The circuit includes a plurality of L1 L2 latches connected in a chain, each L1 L2 latch includes an L1 latch and an L2 latch with the L2 latch having a connected output monitored for a flip. A single L2 detect circuit exclusive OR (XOR) is connected to each L2 latch. An L2 detect circuit XOR tree includes an input connected to a true output of a respective L2 latch in the chain. An L2 clock (LCK) trigger circuit is connected to an output of the L2 detect circuit XOR tree and is shared across each of the plurality of L1 L2 latches for correcting bit flip errors.