Marvell Semiconductor Apr 2017 - Aug 2017
Senior Design Verification Engineer
Amd Apr 2017 - Aug 2017
Senior Silicon Design Engineer
Marvell Semiconductor Feb 1, 2014 - Mar 2017
Design Verification Engineer
Texas A&M University Feb 2013 - Feb 2014
Student Worker Ii - Open Access Labs
Nvidia May 2013 - Aug 2013
Fpga Verfication Intern
Education:
Texas A&M University 2012 - 2014
Masters, Master of Engineering, Computer Engineering, Engineering
National Institute of Technology, Tiruchirappalli 2008 - 2012
Bachelors, Bachelor of Technology, Electronics Engineering
Skills:
C C++ Cuda Verilog Vhdl Systemc Cadence Virtuoso Cadence Spectre Synopsys Tools Soc Matlab Microsoft Office Html Xilinx Impact Xilinx Identify Debugger Computer Architecture Modelsim Field Programmable Gate Arrays Very Large Scale Integration Fpga Vlsi Xilinx
Department of Computer Science, The University of Texas at Dallas
Jan 2012 to 2000 Graduate Research AssistantThe University of Texas at Dallas Richardson, TX Sep 2010 to Jan 2012 Graduate Teaching AssistantReputation.com Redwood City, CA Jun 2010 to Aug 2010 Software Engineering Intern
Education:
The University of Texas at Dallas Richardson, TX 2010 to 2013 Doctor of Philosophy in Computer EngineeringThe University of Texas at Dallas Richardson, TX 2007 to 2009 MS in Computer EngineeringMaulana Azad National Institute of Technology Bhopal, Madhya Pradesh 2003 to 2007 B.Tech in Electronics and Communication Engineering
Skills:
Algorithms, Data Structures, Programming, Research
Department of Computer Science, The University of Texas at Dallas
Jan 2012 to 2000 Graduate Research AssistantThe University of Texas at Dallas Richardson, TX Sep 2010 to Jan 2012 Graduate Teaching AssistantReputation Defender Inc. Redwood City, CA Jun 2010 to Aug 2010 Software Engineering Intern
Education:
The University of Texas at Dallas Richardson, TX 2010 to 2013 PhD in Computer EngineeringThe University of Texas at Dallas Richardson, TX 2007 to 2009 Master of Science in Computer EngineeringMaulana Azad National Institute of Technology Bhopal, Madhya Pradesh 2003 to 2007 Bachelor of Technology in Electronics and Communication Engineering
Skills:
Algorithm Design and Implementation, Parallel Programming.
Us Patents
Speculative Loop Iteration Partitioning For Heterogeneous Execution
- San Diego CA, US Han Zhao - Santa Clara CA, US Aravind Natarajan - Sunnyvale CA, US
International Classification:
G06F 9/50
Abstract:
Embodiments include computing devices, apparatus, and methods implemented by the apparatus for implementing speculative loop iteration partitioning (SLIP) for heterogeneous processing devices. A computing device may receive iteration information for a first partition of iterations of a repetitive process and select a SLIP heuristic based on available SLIP information and iteration information for the first partition. The computing device may determine a split value for the first partition using the SLIP heuristic, and partition the first partition using the split value to produce a plurality of next partitions.
Identifying Enhanced Synchronization Operation Outcomes To Improve Runtime Operations
- San Diego CA, US Gheorghe Cascaval - Palo Alto CA, US Han Zhao - Santa Clara CA, US Tushar Kumar - San Jose CA, US Aravind Natarajan - Sunnyvale CA, US Arun Raman - Fremont CA, US
International Classification:
G06F 9/52
Abstract:
Embodiments include computing devices, systems, and methods identifying enhanced synchronization operation outcomes. A computing device may receive a first resource access request for a first resource of a computing device including a first requester identifier from a first computing element of the computing device. The computing device may also receive a second resource access request for the first resource including a second requester identifier from a second computing element of the computing device. The computing device may grant the first computing element access to the first resource based on the first resource access request, and return a response to the second computing element including the first requester identifier as a winner computing element identifier.
Random-Access Disjoint Concurrent Sparse Writes To Heterogeneous Buffers
- San Diego, CA Aravind Natarajan - Sunnyvale CA, US Dario Suarez Gracia - Teruel, ES
International Classification:
G06F 3/06 G06F 12/10
Abstract:
Methods, devices, and non-transitory processor-readable storage media for a computing device to merge concurrent writes from a plurality of processing units to a buffer associated with an application. An embodiment method executed by a processor may include identifying a plurality of concurrent requests to access the buffer that are sparse, disjoint, and write-only, configuring a write-set for each of the plurality of processing units, executing the plurality of concurrent requests to access the buffer using the write-sets, determining whether each of the plurality of concurrent requests to access the buffer is complete, obtaining a buffer index and data via the write-set of each of the plurality of processing units, and writing to the buffer using the received buffer index and data via the write-set of each of the plurality of processing units in response to determining that each of the plurality of concurrent requests to access the buffer is complete.
Flickr
Youtube
tinyML Talks - Aravind Natarajan: Pushing th...
tinyML Talks webcast - recorded July 21, 2020 "Pushing the Limits of U...
Duration:
38m 32s
Aravind Natarajan presents at Cornell's 2017 ...
Finalist Aravind Natarajan.
Duration:
3m 6s
Data Driven Sales & Marketing Using Advanced ...
Crunch your CRM data and convert it to valuable insights. Know in adva...
Duration:
17m 7s
Inauguration of the Every Child A Scientist P...
Inauguration of the Every Child A Scientist Program 2021-2022 26 Septe...
Duration:
1m 4s
An Introduction to Centerfield
In this podcast, Aravind Natarajan is in conversation with Abhishek Th...
Duration:
46m 51s
December Music Season Dec 2021 Concerts - Ka...
Kalyanapuram Aravind Vocal H N Bhaskar Violin Delhi Sairam Mridangam C...