Arjun Gupta

US Patent:

20170069501, Mar 9, 2017

Filed:

Sep 8, 2016

Appl. No.:

15/259996

Inventors:

- Camas WA, US
Ganesh YERUBANDI - Camas WA, US
Arjun GUPTA - Vancouver WA, US

International Classification:

H01L 21/28
H01L 21/265
H01L 27/115

Abstract:

Provided is a split-gate embedded flash memory cell and method for forming the same. The flash memory cell includes split-gate transistors in which the control gate is aligned with respect to the floating gate without the use of a photolithographic patterning operation to pattern the material from which the control gates are formed. An anisotropic blanket etching operation is used to form the floating gates of the split-gate floating gate transistors alongside sidewalls of a sacrificial layer. Local oxidation of silicon (LOCOS) methods are not needed to form the inter-gate dielectric and therefore high integrity is maintained for the floating transistor gates. The floating transistor gates are formed of charge storage material such as silicon nitride, SiNin some embodiments