Arjun Kapoor

US Patent:

8495402, Jul 23, 2013

Filed:

Dec 16, 2010

Appl. No.:

12/969839

Inventors:

Matthew Byom - Campbell CA, US
Vadim Khmelnitsky - Foster City CA, US
Hugo Fiennes - Palo Alto CA, US
Arjun Kapoor - San Francisco CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G06F 1/30
G06F 1/32

US Classification:

713320, 713300, 713502

Abstract:

Systems and methods are disclosed for limiting power consumption of a non-volatile memory (NVM) using a power limiting scheme that distributes a number of concurrent NVM operations over time. This provides a “current consumption cap” that fixes an upper limit of current consumption for the NVM, thereby eliminating peak power events. In one embodiment, power consumption of a NVM can be limited by receiving data suitable for use as a factor in adjusting a current threshold from at least one of a plurality of system sources. The current threshold can be less than a peak current capable of being consumed by the NVM and can be adjusted based on the received data. A power limiting scheme can be used that limits the number of concurrent NVM operations performed so that a cumulative current consumption of the NVM does not exceed the adjusted current threshold.

US Patent:

8522055, Aug 27, 2013

Filed:

Jul 26, 2010

Appl. No.:

12/843438

Inventors:

Matthew Byom - Campbell CA, US
Hugo Fiennes - Palo Alto CA, US
Arjun Kapoor - San Francisco CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G06F 1/26
G06F 1/00
G06F 13/00
F02P 3/02

US Classification:

713300, 713340, 711100, 323371

Abstract:

Systems and methods are disclosed for validating a non-volatile memory (NVM) package for use in an electronic device before it is incorporated into the device. A NVM package may be validated by determining its power consumption profile, and if the profile meets predetermined criteria, that NVM package may be qualified for use in an electronic system. The power consumption profile may be obtained by issuing commands, such as read commands, to the NVM package to simultaneously access each die of the NVM package to invoke a maximum power consumption event. During this event, power consumption by the NVM package can be monitored and analyzed to determine whether the NVM package qualifies for use in an electronic device.

US Patent:

8533558, Sep 10, 2013

Filed:

Nov 29, 2010

Appl. No.:

12/955174

Inventors:

Damian Pablo Yurzola - Santa Clara CA, US
Rajeev Nagabhirava - Santa Clara CA, US
Arjun Kapoor - San Francisco CA, US
Itai Dror - Omer, IL
Annie Chi-San Chang - Sunnyvale CA, US
Peter Hwang - Newark CA, US
Jian Chen - Menlo Park CA, US

Assignee:

Sandisk Technologies Inc. - Plano TX

International Classification:

G06F 11/00

US Classification:

714758, 714766, 714779

Abstract:

A method includes initiating a compression operation to compress data to be stored in a group of storage elements at a memory device that includes an error correction coding (ECC) engine. The method includes selecting one of a first mode of the ECC engine to generate a first number of parity bits and a second mode of the ECC engine to generate a second number of parity bits based on an extent of compression of the data. The method also includes encoding the compressed data to generate parity bits corresponding to the compressed data and storing the compressed data and the parity bits to the group of storage elements according to a page format that includes a data portion and a parity portion. The compressed data is stored in the data portion and at least some of the parity bits are stored in the parity portion.

US Patent:

8533564, Sep 10, 2013

Filed:

Dec 23, 2009

Appl. No.:

12/645700

Inventors:

Damian Pablo Yurzola - Santa Clara CA, US
Rajeev Nagabhirava - Santa Clara CA, US
Arjun Kapoor - San Francisco CA, US
Itai Dror - Omer, IL

Assignee:

Sandisk Technologies Inc. - Plano TX

International Classification:

G06F 11/00

US Classification:

714763, 714784

Abstract:

A controller coupled to a memory array includes an error correction coding (ECC) engine and an ECC enhancement compression module coupled to the ECC engine. The ECC enhancement compression module is configured to receive and compress control data to be provided to the ECC engine to be encoded. Compressed encoded control data generated at the ECC engine is stored as a codeword at the memory array.

US Patent:

8555095, Oct 8, 2013

Filed:

Jul 26, 2010

Appl. No.:

12/843448

Inventors:

Matthew Byom - Campbell CA, US
Vadim Khmelnitsky - Foster City CA, US
Hugo Fiennes - San Francisco CA, US
Arjun Kapoor - San Francisco CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G06F 1/26
G06F 1/32
G06F 13/00
G06F 13/28

US Classification:

713320, 713300, 711167, 711168, 711169

Abstract:

Systems and methods are disclosed for limiting power consumption of a non-volatile memory (NVM) using a power limiting scheme that distributes a number of concurrent NVM operations over time. This provides a “current consumption cap” that fixes an upper limit of current consumption for the NVM, thereby eliminating peak power events. In one embodiment, power consumption of a NVM can be limited by receiving data suitable for use as a factor in adjusting a current threshold from at least one of a plurality of system sources. The current threshold can be less than a peak current capable of being consumed by the NVM and can be adjusted based on the received data. A power limiting scheme can be used that limits the number of concurrent NVM operations performed so that a cumulative current consumption of the NVM does not exceed the adjusted current threshold.

US Patent:

8583947, Nov 12, 2013

Filed:

Dec 16, 2010

Appl. No.:

12/969833

Inventors:

Matthew Byom - Campbell CA, US
Vadim Khmelnitsky - Foster City CA, US
Hugo Fiennes - Palo Alto CA, US
Arjun Kapoor - San Francisco CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G06F 1/30
G06F 1/32

US Classification:

713300, 713320

Abstract:

Systems and methods are disclosed for limiting power consumption of a non-volatile memory (NVM) using a power limiting scheme that distributes a number of concurrent NVM operations over time. This provides a “current consumption cap” that fixes an upper limit of current consumption for the NVM, thereby eliminating peak power events. In one embodiment, power consumption of a NVM can be limited by receiving data suitable for use as a factor in adjusting a current threshold from at least one of a plurality of system sources. The current threshold can be less than a peak current capable of being consumed by the NVM and can be adjusted based on the received data. A power limiting scheme can be used that limits the number of concurrent NVM operations performed so that a cumulative current consumption of the NVM does not exceed the adjusted current threshold.

US Patent:

20090040842, Feb 12, 2009

Filed:

Aug 6, 2007

Appl. No.:

11/890708

Inventors:

Steven T. Sprouse - San Jose CA, US
Dhaval Parikh - Santa Clara CA, US
Arjun Kapoor - San Francisco CA, US

International Classification:

G11C 7/00

US Classification:

36518916

Abstract:

In a non-volatile memory (NVM) device having a controller and a non-volatile memory array controlled by the controller a voltage supervisor circuit monitors an output of a voltage supply powering the NVM device. The voltage supervisor circuit may be part of the NVM device or coupled to it. The voltage supervisor circuit is configured to assert a “low-voltage” signal responsive to detecting the output of the voltage supply powering the NVM device dropping below a predetermined value. The controller is configured to write data into the memory array while the “low-voltage” signal is deasserted and to suspend writing data while the “low-voltage” signal is asserted. In response to assertion of the “low-voltage” signal, the controller completes a write cycle/program operation, if pending, and prevents any additional write cycles/program operation(s) during assertion of the “low-voltage” signal.

US Patent:

20090040843, Feb 12, 2009

Filed:

Aug 6, 2007

Appl. No.:

11/890734

Inventors:

Steven T. Sprouse - San Jose CA, US
Dhaval Parikh - Santa Clara CA, US
Arjun Kapoor - San Francisco CA, US

International Classification:

G11C 7/00

US Classification:

36518916

Abstract:

In a non-volatile memory (NVM) device having a controller and a non-volatile memory array controlled by the controller a voltage supervisor circuit monitors an output of a voltage supply powering the NVM device. The voltage supervisor circuit may be part of the NVM device or coupled to it. The voltage supervisor circuit is configured to assert a “low-voltage” signal responsive to detecting the output of the voltage supply powering the NVM device dropping below a predetermined value. The controller is configured to write data into the memory array while the “low-voltage” signal is deasserted and to suspend writing data while the “low-voltage” signal is asserted. In response to assertion of the “low-voltage” signal, the controller completes a write cycle/program operation, if pending, and prevents any additional write cycles/program operation(s) during assertion of the “low-voltage” signal.