Arne W Ballantine from Incline Village, NV, age 57

Us Patents

Vertical Trench-Formed Dual-Gate Fet Device Structure And Method For Creation
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US Patent:

6406962, Jun 18, 2002
Filed:

Jan 17, 2001
Appl. No.:

09/761931
Inventors:

Paul D. Agnello - Wappingers Falls NY
Arne W. Ballantine - Round Lake NY
Ramachandra Divakaruni - Somers NY
Erin C. Jones - Tuckahoe NY
Edward J. Nowak - Essex Junction VT
Jed H. Rankin - S. Burlington VT
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01L 21336
US Classification:

438268, 438284, 438270
Abstract:

The present invention relates to an apparatus and method of forming one or more FETs having a vertical trench-formed double-gate, with a plurality of nitride layers having oxide marker etch-stop layers provided periodically there-through, thereby adapting the FETs to have a plurality of selectable gate lengths. The present invention provides for control and formation of gate lengths scaled down to about 5 nm to about 100 nm, preferably from about 5 nm to about 50 nm. The plurality of pad nitride layers with the oxide etch-stop layers provide for the present FET to be connected to a plurality of contacts having a variety of connection depths corresponding to the gate lengths used, by etching a plurality of via in the pad nitride layers whereby such vias stop at selected ones of the etch-stop layers to provide vias adapted to connect with the selected ones of such contacts. Additional gate material may be deposited over a top surface of the selected plurality of nitride layers to allow for contacts to the gate electrodes of any given FET.

In-Line Electrical Monitor For Measuring Mechanical Stress At The Device Level On A Semiconductor Wafer
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US Patent:

6441396, Aug 27, 2002
Filed:

Oct 24, 2000
Appl. No.:

09/695038
Inventors:

Edward D. Adams - Richmond VT
Arne W. Ballantine - Round Lake NY
Richard S. Kontra - Williston VT
Alain Loiseau - Williston VT
James A. Slinkman - Montpelier VT
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01L 2358
US Classification:

257 48, 257 51
Abstract:

A method is presented for measuring and monitoring the mechanical stress at the device level which occurs intrinsically during the fabrication process or which is induced via extrinsic means. The method applies the fact that the current-voltage (I-V) characteristics of a diode change as the diode is subjected to mechanical stress. The method is applicable to monitoring stress at the microscopic and device levels at various stages in the semiconductor wafer fabrication process. Apparatus for implementing the method is also presented.

Interfacial Oxidation Process For High-K Gate Dielectric Process Integration
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US Patent:

6444592, Sep 3, 2002
Filed:

Jun 20, 2000
Appl. No.:

09/597765
Inventors:

Arne W. Ballantine - Round Lake NY
Douglas A. Buchanan - Cortlandt Manor NY
Eduard A. Cartier - New York NY
Kevin K. Chan - Staten Island NY
Matthew W. Copel - Yorktown Heights NY
Christopher P. DEmic - Ossining NY
Evgeni P. Gousev - Mahopac NY
Fenton Read McFeely - Ossining NY
Joseph S. Newbury - Tarrytown NY
Patrick R. Varekamp - Croton-on-Hudson NY
Theodore H. Zabel - Yorktown Heights NY
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01L 21469
US Classification:

438770
Abstract:

A method for integrating a high-k material into CMOS processing schemes is provided. The method includes forming an interfacial oxide, oxynitride and/or nitride layer on a device region of a semiconductor substrate, said interfacial layer having a thickness of less than 10 ; and (b) forming a high-k dielectric material on said interfacial oxide, oxynitride and/or, nitride layer, said high-k dielectric having a dielectric constant, k, of greater than 8.

Structure And Method For Electrical Method Of Determining Film Conformality
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US Patent:

6445194, Sep 3, 2002
Filed:

Feb 16, 2001
Appl. No.:

09/788084
Inventors:

James W. Adkisson - Jericho VT
Arne W. Ballantine - Round Lake NY
Ralph W. Young - Poughkeepsie NY
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G01R 2726
US Classification:

324662
Abstract:

The invention provides a monitor wafer and a method using the wafer to measure the conformality of dielectric films and in particular, for measuring the sidewall deposition thickness of dielectric films.

Multiple Threshold Voltage Fet Using Multiple Work-Function Gate Materials
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US Patent:

6448590, Sep 10, 2002
Filed:

Oct 24, 2000
Appl. No.:

09/695199
Inventors:

James W. Adkisson - Jericho VT
Arne W. Ballantine - Round Lake NY
Ramachandra Divakaruni - Somers NY
Jeffrey B. Johnson - Essex Junction VT
Erin C. Jones - Tuckahoe NY
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01L 2710
US Classification:

257202, 257390, 438241, 438217
Abstract:

A shorter gate length FET for very large scale integrated circuit chips is achieved by providing a wafer with multiple threshold voltages. Multiple threshold voltages are developed by combining multiple work function gate materials. The gate materials are geometrically aligned in a predetermined pattern so that each gate material is adjacent to other gate materials. A patterned linear array embodiment is developed for a multiple threshold voltage design. The method of forming a multiple threshold voltage FET requires disposing different gate materials in aligned trenches within a semiconductor wafer, wherein each gate material represents a separate work function. The gate materials are arranged to be in close proximity to one another to accommodate small gate length designs.

Double Gate Trench Transistor
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US Patent:

6472258, Oct 29, 2002
Filed:

Nov 13, 2000
Appl. No.:

09/711725
Inventors:

James W. Adkisson - Jericho VT
Paul D. Agnello - Wappingers Falls NY
Arne W. Ballantine - Round Lake NY
Rama Divakaruni - Somers NY
Erin C. Jones - Tuckahoe NY
Jed H. Rankin - S. Burlington VT
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01L 2130
US Classification:

438192, 438157, 438256, 257329, 257347
Abstract:

A field effect transistor is formed with a sub-lithographic conduction channel and a dual gate which is formed by a simple process by starting with a silicon-on-insulator wafer, allowing most etching processes to use the buried oxide as an etch stop. Low resistivity of the gate, source and drain is achieved by silicide sidewalls or liners while low gate to junction capacitance is achieved by recessing the silicide and polysilicon dual gate structure from the source and drain region edges.

Spiral Inductor Semiconducting Device With Grounding Strips And Conducting Vias
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US Patent:

6489663, Dec 3, 2002
Filed:

Jan 2, 2001
Appl. No.:

09/753284
Inventors:

Arne W. Ballantine - Round Lake NY
Robert A. Groves - Highland NY
Michael B. Rice - Colchester VT
Anthony K. Stamper - Williston VT
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01L 2900
US Classification:

257531, 257528, 336 68, 336 84 R, 336200
Abstract:

An integrated semiconducting device comprises a semiconducting substrate, a plurality of grounding strips disposed above the substrate in a lower metal level of the semiconducting device, an inductor positioned in an upper metal level of the semiconducting device, and a plurality of conducting vias connected to and extending away from the grounding strips towards the inductor. The inductor, conducting via, ground strips structure forms a Faraday cage that acts as a shield against electromagnetic radiation. The number and placement of the conductive vias are adjustable and can be optimized based on the relative importance of maximizing the quality factor Q of the inductor or minimizing the capacitance between the inductor and ground.

Generator Control System To Accommodate A Decrease In A Power Grid Voltage
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US Patent:

6498462, Dec 24, 2002
Filed:

Feb 5, 2001
Appl. No.:

09/777156
Inventors:

Arne W. Ballantine - Round Lake NY
Mark R. Torpey - Saratoga Springs NY
Assignee:

Plug Power Inc. - Latham NY
International Classification:

H02P 904
US Classification:

322 8, 322 20, 290 40 B, 307 85
Abstract:

A system includes a generator and a circuit. The generator is coupled to provide power to a power grid. The circuit is coupled to the generator and is adapted to use a scheme to detect a shut down of the power grid and prevent the generator from providing power to the power grid in response to the detection of the shut down of the power grid. The circuit is also adapted to receive an indication to modify the scheme and modify the scheme based on the indication.