Arthur L Levin

US Patent:

45905509, May 20, 1986

Filed:

Jun 29, 1983

Appl. No.:

6/509128

Inventors:

John H. Eilert - Wappingers Falls NY
Arthur L. Levin - Pleasant Valley NY
Thomas Julian - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1134

US Classification:

364200

Abstract:

The disclosure provides an embedded hardware/software monitor for a data processing system. It embeds and distributes a plurality of instrumentation table units (ITUs) within various hardware entities in the system to collect sampled hardware signals local in the hardware entity in which the respective ITU is embedded, e. g. in each CPU, I/O processor, system controller, main storage controller, etc. Instrumentation measurement is controlled centrally in the system. Sampling of the system signals is done periodically at a low-rate relative to the CPU machine cycle rate, and the sampled signal are collected in the ITUs for instrumentation analysis. Sampling pulses are synchronously provided in all ITUs in the system. The ITU collected hardware signals are related to software controlled trace entries made in a trace table (TT) in main storage by each CPU in the system executing tracing and other predetermined instructions. An asynchronous relationship between the TT entries and the ITU entries is bridged by the intervening table, called SAT, located in storage.

US Patent:

48211788, Apr 11, 1989

Filed:

Aug 15, 1986

Appl. No.:

6/896994

Inventors:

Arthur L. Levin - Pleasant Valley NY
Don W. Rain - Poughkeepsie NY
David J. Thomas - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 900

US Classification:

364200

Abstract:

The disclosure provides event-controlled operations for an internal hardware/softward monitor for a processor in a data processing system. It embeds and distributes in each processor at least one instrumentation table unit (ITU) and event detection circuitry to detect events and conditions for collecting event-sampled hardware signals provided in the processor hardware in which the respective ITU is embedded. Instrumentation measurement is controlled centrally in the system. Sampling of the CPU signals for recording in the ITU is done at (or a sub-multiple of) the occurrence rate of the selected event(s) in the processor. The sampled signals are recorded in the ITU. The ITUs of plural processors are asynchronously operated in a system. The event-driven monitoring circuitry may be solely provided in an ITU, or it may be superimposed on a timer-driven internal instrumentation system of the type described in U. S. Pat. No. 4,590,550 in which the ITU is shared between event and timer driven modes of operation.

US Patent:

44970226, Jan 29, 1985

Filed:

Oct 19, 1982

Appl. No.:

6/435192

Inventors:

Roger L. Cormier - Pleasant Valley NY
Robert J. Dugan - Hyde Park NY
Richard R. Guyette - Hopewell Junction NY
Ronald L. Hankison - Poughkeepsie NY
Ming C. Hao - Chappaqua NY
Arthur L. Levin - Pleasant Valley NY
George A. McClain - Delray Beach FL
Paul J. Wanish - Poughkeepsie NY
Carl Zeitler - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 300

US Classification:

364200

Abstract:

A channel for a data processing system is provided with a time of day clock that is synchronized with the time of day clock of the associated central processor. Both the central processor and the channel processor record times of particular events, and the channel uses these times to calculate two times called Function Pending and Function Active. Both times begin when the central processor executes an instruction to begin an I/O operation. Function Pending ends when the channel has made successful initial selection. This time shows delays by the channel processor in scheduling the channel control unit, and device resources for I/O operations. Function Active ends at Channel End. A new instruction, Set Channel Monitor, enables or disables these measurements. An information block for each subchannel defines one of several measurement modes for a subchannel or disables the subchannel from measurement.

US Patent:

45983640, Jul 1, 1986

Filed:

Jun 29, 1983

Appl. No.:

6/509129

Inventors:

Peter H. Gum - Poughkeepsie NY
Arthur L. Levin - Pleasant Valley NY
Ronald M. Smith - Wappingers Falls NY
John H. Wilson - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1130

US Classification:

364300

Abstract:

The disclosure describes a separate trace table for each CPU in an MP to avoid inter-CPU interference in making trace table entries for explicit and implicit tracing instructions enabled by flag bits in a control register (CR). Explicit tracing entries are made for an enabled explicit tracing instruction. Implicit tracing entries are made for predetermined instructions (when enabled for tracing) which do not have tracing as their primary purpose. A storage operand of the trace instruction contains a disablement field and optionally may contain an enablement-controlling class field to improve the integrity of traceable programs. A time stamp and range of general register contents is provided in each trace table entry for a tracing instruction. The time stamp enables all trace tables in an MP system to be later merged into a single trace table whenever required.