Arthur K. Lin - Phoenix AZ Robert A. Anderson - Elkgrove CA Kuljeet Singh - Orangevale CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 2302
US Classification:
257678, 257684, 257687
Abstract:
An apparatus and method for dissipating static electrical charge following a manufacturing operation is disclosed. A semiconductor package is provided with ground pads that are located to assure electrical contact with ejection pins used to translate the package from one position to another. Static electricity builds up on the semiconductor package. The ejection pins provide the pathway for dissipating static electrical charge out of the semiconductor package.
Method Of Dissipating Static Electric Charge From A Chip Assembly During A Manufacturing Operation
Arthur K. Lin - Phoenix AZ Robert A. Anderson - Elkgrove CA Kuljeet Singh - Orangevale CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 2144
US Classification:
438106, 438121
Abstract:
An apparatus and method for dissipating static electrical charge following a manufacturing operation is disclosed. A semiconductor package is provided with ground pads that are located to assure electrical contact with ejection pins used to translate the package from one position to another. Static electricity builds up on the semiconductor package. The ejection pins provide the pathway for dissipating static electrical charge out of the semiconductor package.
Charan K. Gurumurthy - Chandler AZ, US Hamid Azimi - Chandler AZ, US Arthur K. Lin - Phoenix AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L021/82
US Classification:
438128, 438129, 438612, 438614, 438674
Abstract:
A method of forming an integrated circuit substrate that may be adapted to be attached to one or more electronic components. The method includes applying a resist to a back side of a substrate which includes patterned conductive layers on a front side and a back side of the substrate. The method further includes removing part of the patterned conductive layer from the front side of the substrate to form pads and interconnects on the front side of the substrate and applying another resist to the front side of the substrate. The method also includes forming a pattern in each resist that exposes the pads on the front and back sides of the substrate and applying electrolytic nickel to the pads on the substrate.
Resumes
Pathfinding Development Supply Chain Engineer And Commodity Manager
Intel Corporation
Pathfinding Development Supply Chain Engineer and Commodity Manager
Aloca Electronic Packaging 1989 - 1996
Asia Customer Application Representative
Interamic 1988 - 1989
R and D Electronic Packaging Engineer
Education:
Uc San Diego
Bachelor of Science In Mechanical Engineering, Bachelors, Engineering
Skills:
Supply Management Cross Functional Team Leadership Spc Manufacturing Global Sourcing Semiconductors Six Sigma Strategic Sourcing Design of Experiments Materials Management Lean Manufacturing Continuous Improvement Supplier Quality Statistical Process Control Supply Chain Dmaic Mrp Procurement Substrates Supply Chain Management Supplier Evaluation
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