Arthur Ronald Sutton

US Patent:

49167030, Apr 10, 1990

Filed:

Nov 28, 1988

Appl. No.:

7/276736

Inventors:

Neal T. Christensen - Wappingers Falls NY
Steven T. Comfort - Poughkeepsie NY
Robert J. Hurban - Old Bethpage NY
Bruce L. McGilvray - Pleasant Valley NY
Arthur J. Sutton - Cold Spring NY
James R. Urquhart - Fishkill NY
David R. Willoughby - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1110
G06F 1130
G06F 1212
G06F 1216

US Classification:

371 511

Abstract:

A method of handling errors in the C bit of a storage key by modifying the INSERT STORAGE KEY (ISK) and the RESET REFERENCE BIT (RRB) instructions. If an error is found in the C bit during the execution of these instructions, microcode is instructed to refresh the C bit. The C bit is interrogated a second time to determine if the refreshed C bit is still in error. If the refreshed C bit is not in error a second time, then the first error was caused by a soft or transient error, and the instruction is continued. If the refreshed C bit is in error a second time then the first and second errors were caused by a permanent error such as a stuck bit, and a system recovery machine check error is generated. The handling of C bit errors is thus done in a dynamic fashion as the instructions are executed.

US Patent:

43420842, Jul 27, 1982

Filed:

Aug 11, 1980

Appl. No.:

6/176827

Inventors:

Gordon S. Sager - Salt Point NY
Arthur J. Sutton - Cold Spring NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1110
G11C 2900

US Classification:

364200

Abstract:

Method and means for validating any BSM in main storage while main storage remains available for normal system operation by all CPUs in the system. The system has plural sets of BSMs in which any set can be operationally fenced from system operation in order to validate any BSM in the fenced set, while the system normally operates with the unfenced set(s) of BSMs comprising main storage. Each BSM set has a BSM controller which is integrated with a hardware BSM tester. All cells in and the addressing circuits to any BSM can be tested by incrementing line addresses through the BSM while comparing a true pattern and then a complement pattern, and then decrementing line addresses through the BSM comparing the complement pattern and then the true pattern. The BSM testers use level sensitive scan design (LSSD) circuits in the BSM controller to serially communicate with a system service processor in response to commands from the service processor and interrupt signals from the BSM tester. A marker mask in each BSM tester permits BSM testing continuity after each interrupt signal.

US Patent:

44307276, Feb 7, 1984

Filed:

Nov 10, 1981

Appl. No.:

6/319869

Inventors:

Brian B. Moore - Poughkeepsie NY
John T. Rodell - Wappingers Falls NY
Arthur J. Sutton - Cold Spring NY
Jeff D. Vowell - Poughkeepsie NY

Assignee:

International Business Machines Corp. - Armonk NY

International Classification:

G06F 1100

US Classification:

364900

Abstract:

This is a system which is used to perform reconfiguration of storage elements in order to permit removal of one or more of the elements for servicing or other reasons. If a storage element that is to be taken off line contains material that is crucial to the continued operation of the system, that material is copied to appropriate areas in other storage elements. After all crucial material has been copied to alternate locations, the original storage element can be taken off line for servicing or other purposes.

US Patent:

52746461, Dec 28, 1993

Filed:

Apr 17, 1991

Appl. No.:

7/686721

Inventors:

Thomas M. Brey - Hyde Park NY
Matthew A. Krygowski - Hopewell Junction NY
Bruce L. McGilvray - Pleasant Valley NY
Trinh H. Nguyen - Wappingers Falls NY
William W. Shen - Poughkeepsie NY
Arthur J. Sutton - Cold Spring NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1110

US Classification:

371 401

Abstract:

A method of automatically invoking a recoverable and fault tolerant implementation of the complemented/recomplemented (C/R) error correction method without the assistance of a service processor when an excessive error is detected in main storage (MS) by ECC logic circuits. An excessive error is not correctable by the ECC. These novel changes to the C/R method increase its effectiveness and protect the C/R hardware against random failure. Further, if an excessive error is corrected in a page in MS, an excessive error reporting process is provided for controlling the reporting using a storage map to determine if a previous correction in that page has been reported. If it has been reported, then no further reporting of soft excessive errors is made for that page. A service processor is signaled in parallel to update its persistent copy of the storage map so that on a next initializations of MS the memory map can be restored in the memory. The memory map is used to assist the repair of failing parts of MS, and is reset after MS is repaired.