Arun Kumar Rao

US Patent:

6697519, Feb 24, 2004

Filed:

Oct 29, 1998

Appl. No.:

09/182070

Inventors:

Arun Rao - San Ramon CA

Assignee:

Pixar - Emeryville CA

International Classification:

G06K 900

US Classification:

382162, 345603, 345589

Abstract:

A system for efficiently converting computer graphics images to film images with accurate color management is described. The system involves the creation of a direct mapping of chromaticity and intensity data from the values used to generate images on a computer monitor to the values used to display the images on projected motion picture film.

US Patent:

6895110, May 17, 2005

Filed:

Oct 30, 2003

Appl. No.:

10/699561

Inventors:

Arun Rao - San Ramon CA, US

Assignee:

Pixar - Emeryville CA

International Classification:

G06K009/00
G06F013/00

US Classification:

382162, 345604

Abstract:

A system for efficiently converting computer graphics images to film images with accurate color management is described. The system involves the creation of a direct mapping of chromaticity and intensity data from the values used to generate images on a computer monitor to the values used to display the images on projected motion picture film.

US Patent:

7155054, Dec 26, 2006

Filed:

Dec 23, 2004

Appl. No.:

11/022165

Inventors:

Arun Rao - San Ramon CA, US

Assignee:

Pixar - Emeryville CA

International Classification:

G06K 9/00
G06F 15/00
G06F 13/00

US Classification:

382162, 358 19

Abstract:

A system for efficiently converting computer graphics images to film images with accurate color management is described. The system involves the creation of a direct mapping of chromaticity and intensity data from the values used to generate images on a computer monitor to the values used to display the images on projected motion picture film.

US Patent:

7271626, Sep 18, 2007

Filed:

Oct 27, 2004

Appl. No.:

10/974177

Inventors:

Alexander Burinskiy - San Jose CA, US
Nathanael Griesert - Grass Valley CA, US
Arun Rao - Rocklin CA, US
William J. McIntyre - Wheatland CA, US
John Philip Parry - Grass Valley CA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H03K 3/00

US Classification:

327108, 327379

Abstract:

A multi-stage transistor circuit is provided in which the multiple transistor stages are coupled in parallel and switched individually in sequence by a series arrangement of buffers. Each buffer drives the gate of a corresponding stage of the multi-stage transistor circuit with a gating signal that is delayed by each buffer. Optionally, the voltage of the gating signal can be varied. Each transistor stage may comprise one or more transistors in parallel. A switched capacitor DC/DC converter incorporating the multi-stage transistor circuit is provided in which parasitic ringing at the output is substantially reduced or eliminated. Additionally, the multi-stage transistor circuit is well suited for implementing an adaptive non-overlapping gating signal generator for complementarily driving a series arrangement of multi-stage transistors. An adaptive gating signal generator incorporating the multi-stage transistor circuit provides the minimum dead time between the gating signals that will ensure under all conditions that the multi-stage transistors will not be on at the same time.

US Patent:

20130120422, May 16, 2013

Filed:

Dec 12, 2011

Appl. No.:

13/323027

Inventors:

Arun RAO - San Ramon CA, US
Frank GRASSIA - Pinole CA, US
Michael O'Brien - Albany CA, US
Michael SHANTZIS - San Francisco CA, US
Paul EDMONDSON - San Francisco CA, US

Assignee:

PIXAR ANIMATION STUDIOS - Emeryville CA

International Classification:

G09G 5/00

US Classification:

345581

Abstract:

A file format that includes a constant section and a varying section. The constant section provides a referencing scheme that references the various components that comprise the scene, as well as a listing of attributes of the scene that are modifiable. Within the same file format, the varying section provides an overriding mechanism to modify the attributes that are available to be modified. Accordingly, the disclosed file format can access cached animated geometry directly and/or aggregate other files via the aforementioned referencing and sparse override semantics. This allows the same set of inspection, manipulation, and rendering tools to be used throughout the rendering pipeline, from asset creation to final rendering.

US Patent:

20210250021, Aug 12, 2021

Filed:

Apr 29, 2021

Appl. No.:

17/244712

Inventors:

- Dallas TX, US
Arun Rao - San Jose CA, US
Joseph Pham - Plano TX, US

International Classification:

H03K 17/0812

Abstract:

Methods, apparatus, systems and articles of manufacture are disclosed to transmit signal in isolated gate drivers. An example apparatus includes a first encoder including: an edge detector coupled to a first sensor; a first clock counter coupled to the edge detector; a first signal selector coupled to the first clock counter; and a first multiplexer including coupled to a signal generator, the first clock counter, and the first signal selector; and a second encoder including: a level detector coupled to a second sensor; a second clock counter coupled to the level detector; a second signal selector coupled to the level detector and the second clock counter; and a second multiplexer coupled to the first multiplexer, a reference voltage, the second signal selector, and a modulator.

US Patent:

20210044294, Feb 11, 2021

Filed:

Oct 28, 2020

Appl. No.:

17/082937

Inventors:

- Dallas TX, US
Shu-Ing Ju - Santa Clara CA, US
Arun Rao - San Jose CA, US
Wei Zhang - Plano TX, US

International Classification:

H03K 17/687
H03K 17/693

Abstract:

Methods, apparatus, systems, and articles of manufacture are disclosed for a multi-level turn-off circuit. An example power delivery circuit includes a two-level turn-off circuit to be coupled to a first switch to reduce a first gate voltage of the first switch from a first voltage to a second voltage when a current flowing through the first switch is greater than an over-current threshold, the two-level turn-off circuit including a second switch, a voltage-current-voltage buffer to reduce a second gate voltage of the second switch from a third voltage to a fourth voltage, and a comparator circuit to turn off the second switch when the second gate voltage is the fourth voltage, and a driver to be coupled to the first switch to turn off the first switch when the second gate voltage is the fourth voltage.

US Patent:

20210028775, Jan 28, 2021

Filed:

Oct 15, 2020

Appl. No.:

17/071803

Inventors:

- Dallas TX, US
Wenxiao Tan - Plano TX, US
Arun Rao - San Jose CA, US

International Classification:

H03K 4/48

Abstract:

Aspects provide for a circuit including a voltage supply, a driver, and a feedback bias circuit. The driver includes a first p-type field effect transistor (FET) and a first n-type FET. The voltage supply has an input and an output. The driver has a first input coupled to the voltage supply output, a second input coupled to a first node, and an output coupled to a second node. The first p-type FET has a gate coupled to the output of the driver, a source coupled to the voltage supply output, and a drain coupled to the second node. The first n-type FET has a gate coupled to the output of the second driver, a drain coupled to the second node, and a source coupled to a ground node. The feedback bias circuit has an input coupled to the second node and an output coupled to the voltage supply input.