Arvind Kumar

US Patent:

6668335, Dec 23, 2003

Filed:

Aug 31, 2000

Appl. No.:

09/653643

Inventors:

Scott E. Breach - Sunnyvale CA
John Eble - Worcester MA
Arvind Kumar - Boston MA
Richard E. Kessler - Shrewsbury MA
Darrel Donaldson - Lancaster MA
David W. Hartwell - Bolton MA

Assignee:

Hewlett-Packard Company, L.P. - Houston TX

International Classification:

G06F 104

US Classification:

713600, 709237, 716 13

Abstract:

A system comprising a communications link between processors configured to transmit packets between transmitting and receiving processors. The communications link comprises a conduction path for each bit in the packet and the paths are grouped into separate bundles and routed along different paths. A forwarded clock signal is sent with each bundle. The processors operate with a clock frequency that is roughly three times as fast as the clock frequency of the forwarded clock signal. Data is transmitted on both rising and falling edges of the clock. The receiving processor comprises a recovery circuit to which it pulls the asynchronous data into the processor clock domain. The recovery circuit comprises a delay locked loop circuit configured to create a delayed copy of the clock signal with clock edges that are aligned with the center of the data window for the transmitted data.

US Patent:

20210312972, Oct 7, 2021

Filed:

Jun 16, 2021

Appl. No.:

17/349854

Inventors:

Arvind A. Kumar - Palo Alto CA, US
James Alexander McCall - Portland OR, US
Bill H. Nale - Livermore CA, US
John R. Goles - Folsom CA, US

International Classification:

G11C 11/4076
G11C 11/4093
G11C 11/4074
G11C 11/4072

Abstract:

A method, apparatus and system. The method includes: performing one or more training iterations to tune a target clock signal frequency to be applied at a memory device, each of the one or more training iterations including: causing a modified clock signal frequency to be applied at the memory device; and decoding a quality feedback message from the memory device including an indication of a performance of the clock signal frequency at the memory device; and in response to a determination that the performance of the clock signal frequency falls within a target performance range of the memory device and that the clock signal frequency is below the target clock signal frequency, performing a subsequent training iteration of the one or more training iterations, and otherwise causing application at the memory device, during a memory operation, of a highest clock signal frequency corresponding to a training iteration for which performance of the clock signal was within the target performance range.

US Patent:

20180095927, Apr 5, 2018

Filed:

Nov 22, 2017

Appl. No.:

15/821401

Inventors:

- Santa Clara CA, US
Darren S. Jue - Sunnyvale CA, US
Rahul C. Shah - San Francisco CA, US
Arvind A. Kumar - Brookline MA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/42
H04L 12/933
G06F 9/30
G06F 9/445
G06F 9/46
G06F 13/40
H04L 12/46
H04L 12/741

Abstract:

A serial data link is to be adapted during initialization of the link. Adaptation of the link is to include receiving a pseudorandom binary sequence (PRBS) from a remote agent, analyzing the PRBS to identify characteristics of the data link, and generating metric data describing the characteristics.

US Patent:

20160211295, Jul 21, 2016

Filed:

Jan 20, 2015

Appl. No.:

14/601010

Inventors:

- Santa Clara CA, US
Duli Mao - Sunnyvale CA, US
Yuanwei Zheng - San Jose CA, US
Chih-Wei Hsiung - San Jose CA, US
Arvind Kumar - Fremont CA, US
Dyson H. Tai - San Jose CA, US

International Classification:

H01L 27/146

Abstract:

A back side illuminated image sensor includes a semiconductor material having a front side and a back side. The semiconductor material is disposed between image sensor circuitry and a light filter array. The image sensor circuitry is disposed on the front side, and the light filter array is disposed proximate to the back side. The image sensor includes a first pixel with a first doped region that extends from the image sensor circuitry into the semiconductor material a first depth. The first pixel also includes a second doped region that is disposed between the back side of the semiconductor material and the first doped region. The second doped region is electrically isolated from the first doped region. A second pixel with a third doped region is also included in the image sensor. The third doped region extends from the image sensor circuitry into the semiconductor material a second depth.

US Patent:

20150067207, Mar 5, 2015

Filed:

Nov 12, 2014

Appl. No.:

14/538897

Inventors:

- Santa Clara CA, US
Darren S. Jue - Sunnyvale CA, US
Rahul Shah - Marlborough MA, US
Arvind Kumar - Palo Alto CA, US

International Classification:

G06F 13/42
G06F 9/30

US Classification:

710105

Abstract:

A serial data link is to be adapted during initialization of the link. Adaptation of the link is to include receiving a pseudorandom binary sequence (PRBS) from a remote agent, analyzing the PRBS to identify characteristics of the data link, and generating metric data describing the characteristics.