Arvind Kumar

US Patent:

6370072, Apr 9, 2002

Filed:

Nov 30, 2000

Appl. No.:

09/726377

Inventors:

Robert H. Dennard - New Rochelle NY
Arvind Kumar - New York NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 702

US Classification:

365210, 365203

Abstract:

In a DRAM memory circuit, a current sensing amplifier is provided that exploits the low impedance of a reference transistor biased in the sub-threshold regime to enable transfer of a small voltage swing on the bitline to result in a large voltage signal on a low capacitance sense node. Compared to conventional voltage sensing, reduced bitline-bitline coupling noise results because of the small bitline swing, potentially allowing more cells to be served by a sense amplifier because of weak dependence of sense amplifier on bit-line capacitance. Compared to previous current-sensing schemes, this invention allows no idling current. The current-sensing amplifier additionally may be used in conjunction with a hierarchical bitline scheme to further increase the number of cells served by each sense amplifier.

US Patent:

6445032, Sep 3, 2002

Filed:

May 4, 1998

Appl. No.:

09/072293

Inventors:

Arvind Kumar - New York NY
Sandip Tiwari - Ossining NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29788

US Classification:

257321, 257315, 257366

Abstract:

A semiconductor memory and a method of producing the memory, includes a transistor including a first gate having an oxide, and a channel, and a back-plane including a second gate and an oxide thereover, the second gate formed opposite to the channel of the transistor, the second gate including a floating gate, wherein a thickness of the oxide of the back-plane is separately scalable from an oxide of the first gate of the transistor.

US Patent:

7417288, Aug 26, 2008

Filed:

Dec 19, 2005

Appl. No.:

11/311462

Inventors:

Robert H. Dennard - New Rochelle NY, US
Wilfried E. Haensch - Somers NY, US
Arvind Kumar - New York NY, US
Robert J. Miller - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/76

US Classification:

257365, 257347, 257366, 257E27098, 365182

Abstract:

A semiconductor structure that includes at least one logic device region and at least one static random access memory (SRAM) device region wherein each device region includes a double gated field effect transistor (FET) wherein the back gate of each of the FET devices is doped to a specific level so as to improve the performance of the FET devices within the different device regions is provided. In particular, the back gate within the SRAM device region is more heavily doped than the back gate within the logic device region. In order to control short channel effects, the FET device within the logic device region includes a doped channel, while the FET device within the SRAM device region does not. A none uniform lateral doping profile with a low net doping beneath the source/drain regions and a high net doping underneath the channel would provide additional SCE control for the logic device.

US Patent:

7718496, May 18, 2010

Filed:

Oct 30, 2007

Appl. No.:

11/927964

Inventors:

Martin M. Frank - Dobbs Ferry NY, US
Arvind Kumar - Chappaqua NY, US
Vijay Narayanan - New York NY, US
Vamsi K. Paruchuri - Albany NY, US
Jeffrey Sleight - Ridgefield CT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/8234
H01L 21/8244

US Classification:

438275, 438595, 257E2164

Abstract:

Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a second nFET region, and a first and a second pFET region; a logic nFET on the substrate over the first nFET region; a logic pFET on the substrate over the first pFET region; a SRAM nFET on the substrate over the second nFET region; and a SRAM pFET on the substrate over the second pFET region, each comprising a gate stack having a metal layer over a high-K layer. The logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET.

US Patent:

8212322, Jul 3, 2012

Filed:

Mar 9, 2010

Appl. No.:

12/720354

Inventors:

Martin M. Frank - Dobbs Ferry NY, US
Arvind Kumar - Chappaqua NY, US
Vijay Narayanan - New York NY, US
Vamsi K. Paruchuri - Albany NY, US
Jeffrey Sleight - Ridgefield CT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/8234
H01L 21/8244

US Classification:

257392, 257391, 257487, 257491, 257500, 257E27098, 257E21661, 438154, 438199, 438261, 438275, 438287, 438591

Abstract:

Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a second nFET region, and a first and a second pFET region; a logic nFET on the substrate over the first nFET region; a logic pFET on the substrate over the first pFET region; a SRAM nFET on the substrate over the second nFET region; and a SRAM pFET on the substrate over the second pFET region, each comprising a gate stack having a metal layer over a high-K layer. The logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET.

US Patent:

20120079160, Mar 29, 2012

Filed:

Sep 24, 2010

Appl. No.:

12/890252

Inventors:

VENKATRAMAN IYER - Austin TX, US
Arvind Kumar - Brookline MA, US
Santanu Chaudhuri - Mountain View CA, US
Darren S. Jue - Sunnyvale CA, US
Dennis R. Halicki - Hillsboro OR, US

International Classification:

G06F 13/36

US Classification:

710311

Abstract:

A method and system to adapt communication links statically and/or dynamically to their individual link conditions on a platform. The communicatively coupled devices have logic to adapt one or more settings of a respective one or more communication links with another device based at least in part on a respective metric of received data patterns from the respective one or more communication links. The communicatively coupled devices in the platform have a back channel to allow feedback or information to be sent from one receiving device to a transmitting device in one embodiment of the invention.

US Patent:

20120181610, Jul 19, 2012

Filed:

Mar 29, 2012

Appl. No.:

13/433815

Inventors:

Martin M. Frank - Dobbs Ferry NY, US
Arvind Kumar - Chappaqua NY, US
Vijay Narayanan - New York NY, US
Vamsi K. Paruchuri - Albany NY, US
Jeffrey Sleight - Ridgefield CT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 27/092

US Classification:

257351, 257369, 257392, 257E27062

Abstract:

Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a second nFET region, and a first and a second pFET region; a logic nFET on the substrate over the first nFET region; a logic pFET on the substrate over the first pFET region; a SRAM nFET on the substrate over the second nFET region; and a SRAM pFET on the substrate over the second pFET region, each comprising a gate stack having a metal layer over a high-K layer. The logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET.

US Patent:

62486268, Jun 19, 2001

Filed:

Jul 17, 1998

Appl. No.:

9/116987

Inventors:

Arvind Kumar - New York NY
Sandip Tiwari - Ossining NY

Assignee:

International Business Machines Corporation

International Classification:

H01L 2176
H01L 2130

US Classification:

438257

Abstract:

A semiconductor memory and a method of producing the memory, includes a transistor including a first gate having an oxide, and a channel, and a back-plane including a second gate and an oxide thereover, the second gate formed opposite to the channel of the transistor, the second gate including a floating gate, wherein a thickness of the oxide of the back-plane is separately scalable from an oxide of the first gate of the transistor.