Arvind Kumar

US Patent:

6337497, Jan 8, 2002

Filed:

May 16, 1997

Appl. No.:

08/858486

Inventors:

Hussein Ibrahim Hanafi - Goldens Bridge NY
Arvind Kumar - New York NY
Matthew R. Wordeman - Mahopac NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 31119

US Classification:

257306, 257310, 257330, 345182

Abstract:

New arrangement of a vertical field effect transistor and a capacitor together forming a memory cell which in turn may be the basic building block of a memory chip, such as a very high density DRAM. The capacitors first electrode is connected to the drain of the transistor. The transistors source is connected to the sources of other transistors, the gate is connected to a word line, and the second electrode of said capacitor is connected to a bit line.

US Patent:

6370072, Apr 9, 2002

Filed:

Nov 30, 2000

Appl. No.:

09/726377

Inventors:

Robert H. Dennard - New Rochelle NY
Arvind Kumar - New York NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 702

US Classification:

365210, 365203

Abstract:

In a DRAM memory circuit, a current sensing amplifier is provided that exploits the low impedance of a reference transistor biased in the sub-threshold regime to enable transfer of a small voltage swing on the bitline to result in a large voltage signal on a low capacitance sense node. Compared to conventional voltage sensing, reduced bitline-bitline coupling noise results because of the small bitline swing, potentially allowing more cells to be served by a sense amplifier because of weak dependence of sense amplifier on bit-line capacitance. Compared to previous current-sensing schemes, this invention allows no idling current. The current-sensing amplifier additionally may be used in conjunction with a hierarchical bitline scheme to further increase the number of cells served by each sense amplifier.

US Patent:

6668335, Dec 23, 2003

Filed:

Aug 31, 2000

Appl. No.:

09/653643

Inventors:

Scott E. Breach - Sunnyvale CA
John Eble - Worcester MA
Arvind Kumar - Boston MA
Richard E. Kessler - Shrewsbury MA
Darrel Donaldson - Lancaster MA
David W. Hartwell - Bolton MA

Assignee:

Hewlett-Packard Company, L.P. - Houston TX

International Classification:

G06F 104

US Classification:

713600, 709237, 716 13

Abstract:

A system comprising a communications link between processors configured to transmit packets between transmitting and receiving processors. The communications link comprises a conduction path for each bit in the packet and the paths are grouped into separate bundles and routed along different paths. A forwarded clock signal is sent with each bundle. The processors operate with a clock frequency that is roughly three times as fast as the clock frequency of the forwarded clock signal. Data is transmitted on both rising and falling edges of the clock. The receiving processor comprises a recovery circuit to which it pulls the asynchronous data into the processor clock domain. The recovery circuit comprises a delay locked loop circuit configured to create a delayed copy of the clock signal with clock edges that are aligned with the center of the data window for the transmitted data.

US Patent:

7417288, Aug 26, 2008

Filed:

Dec 19, 2005

Appl. No.:

11/311462

Inventors:

Robert H. Dennard - New Rochelle NY, US
Wilfried E. Haensch - Somers NY, US
Arvind Kumar - New York NY, US
Robert J. Miller - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/76

US Classification:

257365, 257347, 257366, 257E27098, 365182

Abstract:

A semiconductor structure that includes at least one logic device region and at least one static random access memory (SRAM) device region wherein each device region includes a double gated field effect transistor (FET) wherein the back gate of each of the FET devices is doped to a specific level so as to improve the performance of the FET devices within the different device regions is provided. In particular, the back gate within the SRAM device region is more heavily doped than the back gate within the logic device region. In order to control short channel effects, the FET device within the logic device region includes a doped channel, while the FET device within the SRAM device region does not. A none uniform lateral doping profile with a low net doping beneath the source/drain regions and a high net doping underneath the channel would provide additional SCE control for the logic device.

US Patent:

7718496, May 18, 2010

Filed:

Oct 30, 2007

Appl. No.:

11/927964

Inventors:

Martin M. Frank - Dobbs Ferry NY, US
Arvind Kumar - Chappaqua NY, US
Vijay Narayanan - New York NY, US
Vamsi K. Paruchuri - Albany NY, US
Jeffrey Sleight - Ridgefield CT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/8234
H01L 21/8244

US Classification:

438275, 438595, 257E2164

Abstract:

Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a second nFET region, and a first and a second pFET region; a logic nFET on the substrate over the first nFET region; a logic pFET on the substrate over the first pFET region; a SRAM nFET on the substrate over the second nFET region; and a SRAM pFET on the substrate over the second pFET region, each comprising a gate stack having a metal layer over a high-K layer. The logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET.

US Patent:

7838942, Nov 23, 2010

Filed:

Jun 23, 2008

Appl. No.:

12/144272

Inventors:

Robert H. Dennard - Croton on Hudson NY, US
Wilfried E. Haensch - Somers NY, US
Arvind Kumar - Chappaqua NY, US
Robert J. Miller - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/76

US Classification:

257365, 257288, 257347, 257366, 257E27096, 365182

Abstract:

A semiconductor structure that includes at least one logic device region and at least one static random access memory (SRAM) device region wherein each device region includes a double gated field effect transistor (FET) wherein the back gate of each of the FET devices is doped to a specific level so as to improve the performance of the FET devices within the different device regions is provided. In particular, the back gate within the SRAM device region is more heavily doped than the back gate within the logic device region. In order to control short channel effects, the FET device within the logic device region includes a doped channel, while the FET device within the SRAM device region does not. A none uniform lateral doping profile with a low net doping beneath the source/drain regions and a high net doping underneath the channel would provide additional SCE control for the logic device.

US Patent:

8030145, Oct 4, 2011

Filed:

Jan 8, 2010

Appl. No.:

12/684225

Inventors:

Leland Chang - Yorktown Heights NY, US
Brian L. Ji - Yorktown Heights NY, US
Arvind Kumar - Hopewell Junction NY, US
Amlan Majumdar - Yorktown Heights NY, US
Katherine Saenger - Yorktown Heights NY, US
Leathen Shi - Yorktown Heights NY, US
Jeng-Bang Yau - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/84

US Classification:

438157, 438458, 257E21421

Abstract:

A fully depleted semiconductor-on-insulator (FDSOI) transistor structure includes a back gate electrode having a limited thickness and aligned to a front gate electrode. The back gate electrode is formed in a first substrate by ion implantation of dopants through a first oxide cap layer. Global alignment markers are formed in the first substrate to enable alignment of the front gate electrode to the back gate electrode. The global alignment markers enable preparation of a virtually flat substrate on the first substrate so that the first substrate can be bonded to a second substrate in a reliable manner.

US Patent:

8212322, Jul 3, 2012

Filed:

Mar 9, 2010

Appl. No.:

12/720354

Inventors:

Martin M. Frank - Dobbs Ferry NY, US
Arvind Kumar - Chappaqua NY, US
Vijay Narayanan - New York NY, US
Vamsi K. Paruchuri - Albany NY, US
Jeffrey Sleight - Ridgefield CT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/8234
H01L 21/8244

US Classification:

257392, 257391, 257487, 257491, 257500, 257E27098, 257E21661, 438154, 438199, 438261, 438275, 438287, 438591

Abstract:

Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a second nFET region, and a first and a second pFET region; a logic nFET on the substrate over the first nFET region; a logic pFET on the substrate over the first pFET region; a SRAM nFET on the substrate over the second nFET region; and a SRAM pFET on the substrate over the second pFET region, each comprising a gate stack having a metal layer over a high-K layer. The logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET.