Arvind W Kumar

US Patent:

6668335, Dec 23, 2003

Filed:

Aug 31, 2000

Appl. No.:

09/653643

Inventors:

Scott E. Breach - Sunnyvale CA
John Eble - Worcester MA
Arvind Kumar - Boston MA
Richard E. Kessler - Shrewsbury MA
Darrel Donaldson - Lancaster MA
David W. Hartwell - Bolton MA

Assignee:

Hewlett-Packard Company, L.P. - Houston TX

International Classification:

G06F 104

US Classification:

713600, 709237, 716 13

Abstract:

A system comprising a communications link between processors configured to transmit packets between transmitting and receiving processors. The communications link comprises a conduction path for each bit in the packet and the paths are grouped into separate bundles and routed along different paths. A forwarded clock signal is sent with each bundle. The processors operate with a clock frequency that is roughly three times as fast as the clock frequency of the forwarded clock signal. Data is transmitted on both rising and falling edges of the clock. The receiving processor comprises a recovery circuit to which it pulls the asynchronous data into the processor clock domain. The recovery circuit comprises a delay locked loop circuit configured to create a delayed copy of the clock signal with clock edges that are aligned with the center of the data window for the transmitted data.

US Patent:

7327150, Feb 5, 2008

Filed:

Oct 11, 2005

Appl. No.:

11/248775

Inventors:

Arvind Kumar - Brookline MA, US
Kambiz Munshi - Framingham MA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G01R 27/08
G01R 31/26

US Classification:

324691, 324765

Abstract:

For one embodiment, an integrated circuit includes a node to couple one or more components to the integrated circuit to carry current through a package for the integrated circuit. The integrated circuit also includes a monitor to measure a resistance of the package based at least in part on a reference resistance of the package and a resistance of one or more components that are to carry current through the package. For another embodiment, current through one or more components that are to carry current through a package for an integrated circuit is controlled. A resistance of the package is measured based at least in part on a reference resistance of the package and a resistance of one or more components that are to carry current through the package.

US Patent:

7332947, Feb 19, 2008

Filed:

Mar 15, 2005

Appl. No.:

11/082142

Inventors:

Arvind Kumar - Brookline MA, US
Narayanan Natarajan - Shrewsbury MA, US
Mahalingam Nagarajan - Grafton MA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03L 7/06

US Classification:

327150, 331 17

Abstract:

An apparatus for controllably distorting the duty cycle of a clock signal is disclosed. Methods and systems using embodiments of the invention are also described.

US Patent:

20060274874, Dec 7, 2006

Filed:

Jun 1, 2005

Appl. No.:

11/142764

Inventors:

Arvind Kumar - Brookline MA, US
Warren Anderson - Westborough MA, US
George Powley - Northborough MA, US
Jeff Wight - Aloha OR, US

International Classification:

H04L 7/04

US Classification:

375362000

Abstract:

According to some embodiments, a system provides acquisition of a first sample of a data signal based on a first clock signal associated with a first phase, the first sample associated with a first data eye of a clock cycle, acquisition of a second sample of the data signal based on a second clock signal associated with a second phase, the second sample associated with a second data eye of the clock cycle, determination of whether the first sample reflects expected data associated with the first data eye, control of the first phase of the first clock signal based on whether the first sample reflects the expected data associated with the first data eye, determination of whether the second sample reflects expected data associated with the second data eye, and control of the second phase of the second clock signal based on whether the second sample reflects the expected data associated with the second data eye.

US Patent:

20120079160, Mar 29, 2012

Filed:

Sep 24, 2010

Appl. No.:

12/890252

Inventors:

VENKATRAMAN IYER - Austin TX, US
Arvind Kumar - Brookline MA, US
Santanu Chaudhuri - Mountain View CA, US
Darren S. Jue - Sunnyvale CA, US
Dennis R. Halicki - Hillsboro OR, US

International Classification:

G06F 13/36

US Classification:

710311

Abstract:

A method and system to adapt communication links statically and/or dynamically to their individual link conditions on a platform. The communicatively coupled devices have logic to adapt one or more settings of a respective one or more communication links with another device based at least in part on a respective metric of received data patterns from the respective one or more communication links. The communicatively coupled devices in the platform have a back channel to allow feedback or information to be sent from one receiving device to a transmitting device in one embodiment of the invention.

US Patent:

20220199627, Jun 23, 2022

Filed:

Dec 15, 2021

Appl. No.:

17/551903

Inventors:

- Santa Clara CA, US
Arvind KUMAR - Santa Clara CA, US
Sony VARGHESE - Manchester MA, US

International Classification:

H01L 27/108

Abstract:

Examples herein relate to three-dimensional (3D) dynamic random access memory (DRAM) devices and replacement channel processes for fabricating 3D DRAM devices. In an example, a gate dielectric layer is formed on a sacrificial material, and a gate electrode is formed on the gate dielectric layer. After the gate electrode is formed, the sacrificial material is removed and replaced by a semiconductor material. A channel region of a device (e.g., a transistor) that includes the gate dielectric layer and gate electrode is formed in the semiconductor material. The channel region can be vertical or horizontal with respect to a main surface of a substrate on which the device is formed. A capacitor can be formed, such as before or after the semiconductor material is formed, and is electrically connected to the semiconductor material. The device and the capacitor together can form at least part of a 3D DRAM cell.

US Patent:

20210312972, Oct 7, 2021

Filed:

Jun 16, 2021

Appl. No.:

17/349854

Inventors:

Arvind A. Kumar - Palo Alto CA, US
James Alexander McCall - Portland OR, US
Bill H. Nale - Livermore CA, US
John R. Goles - Folsom CA, US

International Classification:

G11C 11/4076
G11C 11/4093
G11C 11/4074
G11C 11/4072

Abstract:

A method, apparatus and system. The method includes: performing one or more training iterations to tune a target clock signal frequency to be applied at a memory device, each of the one or more training iterations including: causing a modified clock signal frequency to be applied at the memory device; and decoding a quality feedback message from the memory device including an indication of a performance of the clock signal frequency at the memory device; and in response to a determination that the performance of the clock signal frequency falls within a target performance range of the memory device and that the clock signal frequency is below the target clock signal frequency, performing a subsequent training iteration of the one or more training iterations, and otherwise causing application at the memory device, during a memory operation, of a highest clock signal frequency corresponding to a training iteration for which performance of the clock signal was within the target performance range.

US Patent:

20210247919, Aug 12, 2021

Filed:

Apr 2, 2021

Appl. No.:

17/221728

Inventors:

- Santa Clara CA, US
Arvind KUMAR - Brookline MA, US
John R. GOLES - Folsom CA, US
Christopher E. COX - Placerville CA, US

International Classification:

G06F 3/06
G06F 11/22
G06F 13/16

Abstract:

In a memory system an interface circuit includes an interface to a memory array, and to a data signal. The circuit includes loopback circuitry to enable loopback of received data signals without having to access the data from the memory array. The circuit can be part of a memory device, a register device, or a data buffer. The circuit interfaces to a memory array of a memory device, and performs loopback functions for a host controller that can test the operation of the interface.