Arvind Kumar

US Patent:

6337497, Jan 8, 2002

Filed:

May 16, 1997

Appl. No.:

08/858486

Inventors:

Hussein Ibrahim Hanafi - Goldens Bridge NY
Arvind Kumar - New York NY
Matthew R. Wordeman - Mahopac NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 31119

US Classification:

257306, 257310, 257330, 345182

Abstract:

New arrangement of a vertical field effect transistor and a capacitor together forming a memory cell which in turn may be the basic building block of a memory chip, such as a very high density DRAM. The capacitors first electrode is connected to the drain of the transistor. The transistors source is connected to the sources of other transistors, the gate is connected to a word line, and the second electrode of said capacitor is connected to a bit line.

US Patent:

6370072, Apr 9, 2002

Filed:

Nov 30, 2000

Appl. No.:

09/726377

Inventors:

Robert H. Dennard - New Rochelle NY
Arvind Kumar - New York NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 702

US Classification:

365210, 365203

Abstract:

In a DRAM memory circuit, a current sensing amplifier is provided that exploits the low impedance of a reference transistor biased in the sub-threshold regime to enable transfer of a small voltage swing on the bitline to result in a large voltage signal on a low capacitance sense node. Compared to conventional voltage sensing, reduced bitline-bitline coupling noise results because of the small bitline swing, potentially allowing more cells to be served by a sense amplifier because of weak dependence of sense amplifier on bit-line capacitance. Compared to previous current-sensing schemes, this invention allows no idling current. The current-sensing amplifier additionally may be used in conjunction with a hierarchical bitline scheme to further increase the number of cells served by each sense amplifier.

US Patent:

6445032, Sep 3, 2002

Filed:

May 4, 1998

Appl. No.:

09/072293

Inventors:

Arvind Kumar - New York NY
Sandip Tiwari - Ossining NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29788

US Classification:

257321, 257315, 257366

Abstract:

A semiconductor memory and a method of producing the memory, includes a transistor including a first gate having an oxide, and a channel, and a back-plane including a second gate and an oxide thereover, the second gate formed opposite to the channel of the transistor, the second gate including a floating gate, wherein a thickness of the oxide of the back-plane is separately scalable from an oxide of the first gate of the transistor.

US Patent:

7417288, Aug 26, 2008

Filed:

Dec 19, 2005

Appl. No.:

11/311462

Inventors:

Robert H. Dennard - New Rochelle NY, US
Wilfried E. Haensch - Somers NY, US
Arvind Kumar - New York NY, US
Robert J. Miller - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/76

US Classification:

257365, 257347, 257366, 257E27098, 365182

Abstract:

A semiconductor structure that includes at least one logic device region and at least one static random access memory (SRAM) device region wherein each device region includes a double gated field effect transistor (FET) wherein the back gate of each of the FET devices is doped to a specific level so as to improve the performance of the FET devices within the different device regions is provided. In particular, the back gate within the SRAM device region is more heavily doped than the back gate within the logic device region. In order to control short channel effects, the FET device within the logic device region includes a doped channel, while the FET device within the SRAM device region does not. A none uniform lateral doping profile with a low net doping beneath the source/drain regions and a high net doping underneath the channel would provide additional SCE control for the logic device.

US Patent:

7718496, May 18, 2010

Filed:

Oct 30, 2007

Appl. No.:

11/927964

Inventors:

Martin M. Frank - Dobbs Ferry NY, US
Arvind Kumar - Chappaqua NY, US
Vijay Narayanan - New York NY, US
Vamsi K. Paruchuri - Albany NY, US
Jeffrey Sleight - Ridgefield CT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/8234
H01L 21/8244

US Classification:

438275, 438595, 257E2164

Abstract:

Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a second nFET region, and a first and a second pFET region; a logic nFET on the substrate over the first nFET region; a logic pFET on the substrate over the first pFET region; a SRAM nFET on the substrate over the second nFET region; and a SRAM pFET on the substrate over the second pFET region, each comprising a gate stack having a metal layer over a high-K layer. The logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET.

US Patent:

7838942, Nov 23, 2010

Filed:

Jun 23, 2008

Appl. No.:

12/144272

Inventors:

Robert H. Dennard - Croton on Hudson NY, US
Wilfried E. Haensch - Somers NY, US
Arvind Kumar - Chappaqua NY, US
Robert J. Miller - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/76

US Classification:

257365, 257288, 257347, 257366, 257E27096, 365182

Abstract:

A semiconductor structure that includes at least one logic device region and at least one static random access memory (SRAM) device region wherein each device region includes a double gated field effect transistor (FET) wherein the back gate of each of the FET devices is doped to a specific level so as to improve the performance of the FET devices within the different device regions is provided. In particular, the back gate within the SRAM device region is more heavily doped than the back gate within the logic device region. In order to control short channel effects, the FET device within the logic device region includes a doped channel, while the FET device within the SRAM device region does not. A none uniform lateral doping profile with a low net doping beneath the source/drain regions and a high net doping underneath the channel would provide additional SCE control for the logic device.

US Patent:

7936042, May 3, 2011

Filed:

Nov 13, 2007

Appl. No.:

11/939017

Inventors:

Arvind Kumar - Beacon NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/02

US Classification:

257487, 257339, 257409, 257616, 257E29039

Abstract:

A field effect transistor comprising a silicon containing body is provided. After formation of a gate dielectric, gate electrode, and a first gate spacer, a drain side trench is formed and filled with a wide band gap semiconductor material. Optionally, a source side trench may be formed and filled with a silicon germanium alloy to enhance an on-current of the field effect transistor. Halo implantation and source and drain ion implantation are performed to form various doped regions. Since the wide band gap semiconductor material as a wider band gap than that of silicon, impact ionization is reduced due to the use of the wide band gap semiconductor material in the drain, and consequently, a breakdown voltage of the field effect transistor is increased compared to transistors employing silicon in the drain region.

US Patent:

7956415, Jun 7, 2011

Filed:

Jun 5, 2008

Appl. No.:

12/133686

Inventors:

Anthony I. Chou - Beacon NY, US
Andres Bryant - Burlington VT, US
Arvind Kumar - Beacon NY, US
Shreesh Narasimha - Beacon NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 27/12

US Classification:

257347

Abstract:

A top semiconductor layer is formed with two different thicknesses such that a step is formed underneath a body region of a semiconductor-on-insulator (SOI) field effect transistor at the interface between a top semiconductor layer and an underlying buried insulator layer. The interface and the accompanying interfacial defects in the body region provide recombination centers, which increase the recombination rate between the holes and electrons in the body region. Optionally, a spacer portion, comprising a material that functions as recombination centers, is formed on sidewalls of the step to provide an enhanced recombination rate between holes and electrons in the body region, which increases the bipolar breakdown voltage of a SOI field effect transistor.