Arvind Kumar

US Patent:

6668335, Dec 23, 2003

Filed:

Aug 31, 2000

Appl. No.:

09/653643

Inventors:

Scott E. Breach - Sunnyvale CA
John Eble - Worcester MA
Arvind Kumar - Boston MA
Richard E. Kessler - Shrewsbury MA
Darrel Donaldson - Lancaster MA
David W. Hartwell - Bolton MA

Assignee:

Hewlett-Packard Company, L.P. - Houston TX

International Classification:

G06F 104

US Classification:

713600, 709237, 716 13

Abstract:

A system comprising a communications link between processors configured to transmit packets between transmitting and receiving processors. The communications link comprises a conduction path for each bit in the packet and the paths are grouped into separate bundles and routed along different paths. A forwarded clock signal is sent with each bundle. The processors operate with a clock frequency that is roughly three times as fast as the clock frequency of the forwarded clock signal. Data is transmitted on both rising and falling edges of the clock. The receiving processor comprises a recovery circuit to which it pulls the asynchronous data into the processor clock domain. The recovery circuit comprises a delay locked loop circuit configured to create a delayed copy of the clock signal with clock edges that are aligned with the center of the data window for the transmitted data.

US Patent:

20220199627, Jun 23, 2022

Filed:

Dec 15, 2021

Appl. No.:

17/551903

Inventors:

- Santa Clara CA, US
Arvind KUMAR - Santa Clara CA, US
Sony VARGHESE - Manchester MA, US

International Classification:

H01L 27/108

Abstract:

Examples herein relate to three-dimensional (3D) dynamic random access memory (DRAM) devices and replacement channel processes for fabricating 3D DRAM devices. In an example, a gate dielectric layer is formed on a sacrificial material, and a gate electrode is formed on the gate dielectric layer. After the gate electrode is formed, the sacrificial material is removed and replaced by a semiconductor material. A channel region of a device (e.g., a transistor) that includes the gate dielectric layer and gate electrode is formed in the semiconductor material. The channel region can be vertical or horizontal with respect to a main surface of a substrate on which the device is formed. A capacitor can be formed, such as before or after the semiconductor material is formed, and is electrically connected to the semiconductor material. The device and the capacitor together can form at least part of a 3D DRAM cell.

US Patent:

20210312972, Oct 7, 2021

Filed:

Jun 16, 2021

Appl. No.:

17/349854

Inventors:

Arvind A. Kumar - Palo Alto CA, US
James Alexander McCall - Portland OR, US
Bill H. Nale - Livermore CA, US
John R. Goles - Folsom CA, US

International Classification:

G11C 11/4076
G11C 11/4093
G11C 11/4074
G11C 11/4072

Abstract:

A method, apparatus and system. The method includes: performing one or more training iterations to tune a target clock signal frequency to be applied at a memory device, each of the one or more training iterations including: causing a modified clock signal frequency to be applied at the memory device; and decoding a quality feedback message from the memory device including an indication of a performance of the clock signal frequency at the memory device; and in response to a determination that the performance of the clock signal frequency falls within a target performance range of the memory device and that the clock signal frequency is below the target clock signal frequency, performing a subsequent training iteration of the one or more training iterations, and otherwise causing application at the memory device, during a memory operation, of a highest clock signal frequency corresponding to a training iteration for which performance of the clock signal was within the target performance range.

US Patent:

20180095927, Apr 5, 2018

Filed:

Nov 22, 2017

Appl. No.:

15/821401

Inventors:

- Santa Clara CA, US
Darren S. Jue - Sunnyvale CA, US
Rahul C. Shah - San Francisco CA, US
Arvind A. Kumar - Brookline MA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/42
H04L 12/933
G06F 9/30
G06F 9/445
G06F 9/46
G06F 13/40
H04L 12/46
H04L 12/741

Abstract:

A serial data link is to be adapted during initialization of the link. Adaptation of the link is to include receiving a pseudorandom binary sequence (PRBS) from a remote agent, analyzing the PRBS to identify characteristics of the data link, and generating metric data describing the characteristics.

US Patent:

20170285774, Oct 5, 2017

Filed:

Apr 1, 2016

Appl. No.:

15/089290

Inventors:

Kunjal Parikh - San Jose CA, US
Thomas Agung Nugraha - Tokyo, JP
Arvind Kumar - Beaverton OR, US
Akihiro Takagi - San Mateo CA, US
John F. Jacobs - San Jose CA, US

International Classification:

G06F 3/0354
G06F 3/01
G06F 3/16
G06F 3/038

Abstract:

An active stylus enables an electronic device to provide a user-friendly user input. The active stylus uses various sensors and feedback mechanisms to characterize or simulate the audible and haptic feedback associated with various writing instruments. The sensors capture pressure, speed, vibration, sound, and other characteristics of using a specific writing instrument on a given surface. This enables the active stylus to simulate the writing instrument accurately while avoiding increased haze and optical distortions due to etching or engineered film.

US Patent:

20170179189, Jun 22, 2017

Filed:

Dec 18, 2015

Appl. No.:

14/974362

Inventors:

- Santa Clara CA, US
Gang Chen - San Jose CA, US
Duli Mao - Sunnyvale CA, US
Dyson Tai - San Jose CA, US
Arvind Kumar - Manchester MA, US
Hung Chih Chang - Newark CA, US
Chih-Wei Hsiung - San Jose CA, US

International Classification:

H01L 27/146

Abstract:

An image sensor includes a plurality of photodiodes arranged in an array and disposed in a semiconductor material with pinning wells disposed between individual photodiodes in the plurality of photodiodes. The image sensor also includes a microlens layer. The microlens layer is disposed proximate to the semiconductor material and is optically aligned with the plurality of photodiodes. A spacer layer disposed between the semiconductor material and the microlens layer. The spacer layer has a concave cross-sectional profile across the array, and the microlens layer is conformal with the concave cross-sectional profile of the spacer layer.

US Patent:

20160227147, Aug 4, 2016

Filed:

Feb 3, 2015

Appl. No.:

14/612961

Inventors:

- Santa Clara CA, US
Dominic Massetti - San Jose CA, US
Chih-Wei Hsiung - San Jose CA, US
Arvind Kumar - Fremont CA, US
Yuanwei Zheng - San Jose CA, US
Duli Mao - Sunnyvale CA, US
Dyson H. Tai - San Jose CA, US

International Classification:

H04N 5/3745
H04N 5/378

Abstract:

A back side illuminated image sensor includes a pixel array including semiconductor material, and image sensor circuitry disposed on a front side of the semiconductor material to control operation of the pixel array. A first pixel includes a first doped region disposed proximate to a back side of the semiconductor material and extends into the semiconductor material a first depth to reach the image sensor circuitry. A second pixel with a second doped region is disposed proximate to the back side of the semiconductor material and extends into the semiconductor material a second depth which is less than the first depth. A third doped region is disposed between the second doped region and the image sensor circuitry front side of the semiconductor material. The third doped region is electrically isolated from the first doped region and the second doped region.

US Patent:

20160211295, Jul 21, 2016

Filed:

Jan 20, 2015

Appl. No.:

14/601010

Inventors:

- Santa Clara CA, US
Duli Mao - Sunnyvale CA, US
Yuanwei Zheng - San Jose CA, US
Chih-Wei Hsiung - San Jose CA, US
Arvind Kumar - Fremont CA, US
Dyson H. Tai - San Jose CA, US

International Classification:

H01L 27/146

Abstract:

A back side illuminated image sensor includes a semiconductor material having a front side and a back side. The semiconductor material is disposed between image sensor circuitry and a light filter array. The image sensor circuitry is disposed on the front side, and the light filter array is disposed proximate to the back side. The image sensor includes a first pixel with a first doped region that extends from the image sensor circuitry into the semiconductor material a first depth. The first pixel also includes a second doped region that is disposed between the back side of the semiconductor material and the first doped region. The second doped region is electrically isolated from the first doped region. A second pixel with a third doped region is also included in the image sensor. The third doped region extends from the image sensor circuitry into the semiconductor material a second depth.