Ashfaq A Shaikh

US Patent:

7323907, Jan 29, 2008

Filed:

Nov 30, 2005

Appl. No.:

11/292228

Inventors:

Ting-Sheng Ku - San Jose CA, US
Ashfaq R. Shaikh - San Jose CA, US

International Classification:

H03K 17/16

US Classification:

326 82, 326 22

Abstract:

Embodiments for controlling pre-emphasis driver circuits for electrical signal interconnects within a computer system are disclosed.

US Patent:

7370170, May 6, 2008

Filed:

Aug 3, 2004

Appl. No.:

10/910050

Inventors:

Ashfaq R. Shaikh - San Jose CA, US
Barry A. Wagner - San Jose CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06F 12/00

US Classification:

711167, 710 52, 710 58, 345563, 345626

Abstract:

Methods and apparatuses that enable memory devices to inform graphical processing systems about the results of WRITE de-skew training. A WRITE-TRAINING mode is added to a memory device. When the WRITE-TRAINING mode is asserted the memory data mask (DM) pin is converted to an output port. Incoming WRITE data is strobed-into the memory device and the resulting data pattern is compared to a desired pattern. If the incoming WRITE data and strobed-in data match, that result is sent to the graphical processing system by setting the DM pin HIGH. If the incoming WRITE data and the strobed-in data do not match, that result is sent to the graphical processing system by setting the DM pin LOW. Beneficially, the incoming data and the desired pattern are derived from pseudo random bit sequence (PRBS) sources.

US Patent:

7411415, Aug 12, 2008

Filed:

Feb 25, 2004

Appl. No.:

10/787923

Inventors:

Ashfaq Shaikh - San Jose CA, US
Ting Ku - San Jose CA, US
Huabo Chen - San Jose CA, US

International Classification:

H03K 17/16

US Classification:

326 30, 326 82, 326 83, 326 86

Abstract:

Embodiments of methods, apparatuses, systems and/or devices associated with a bus termination scheme are disclosed.

US Patent:

7541835, Jun 2, 2009

Filed:

Dec 8, 2005

Appl. No.:

11/299081

Inventors:

Ashfaq R. Shaikh - San Jose CA, US
Chang Hee Hong - Pleasanton CA, US
Ting-Sheng Ku - San Jose CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

H03K 19/00

US Classification:

326 56, 326 57, 326 62, 326 82

Abstract:

Techniques and circuits for ensuring undefined control signals are not inadvertently driven onto a bus due to core logic and I/O logic supply voltages reaching final voltage levels at different times are provided. According to some embodiments, an internal voltage supply sense circuit may monitor a level of a voltage supply that powers core logic that generates control signals to be driven on I/O pads. The sense circuit may generate one or more control signals used to keep I/O pads in a high impedance state.

US Patent:

7567104, Jul 28, 2009

Filed:

Aug 17, 2007

Appl. No.:

11/840503

Inventors:

Ting-Sheng Ku - San Jose CA, US
Ashfaq R. Shaikh - San Jose CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

H03L 7/00

US Classification:

327161, 327141

Abstract:

Circuits, methods, and apparatus for training a phase shift circuit to provide a phase shift for improved data recovery. A specific embodiment of the present invention provides a variable delay cell. A delay through the variable delay cell is changed while training patterns are received. The presence of errors in the received data pattern is tracked, and from the presence or absence of errors a preferred delay is selected and used for receiving data.

US Patent:

7570088, Aug 4, 2009

Filed:

Dec 1, 2005

Appl. No.:

11/293627

Inventors:

Ting-Sheng Ku - San Jose CA, US
Chang Hee Hong - Pleasanton CA, US
Ashfaq R. Shaikh - San Jose CA, US
Shifeng Yu - Fremont CA, US

Assignee:

nVidia Corporation - Santa Clara CA

International Classification:

H03K 3/00

US Classification:

327112, 326 81, 326 87

Abstract:

Embodiments for providing a plurality of bias voltages to input/output circuitry are disclosed.

US Patent:

7619444, Nov 17, 2009

Filed:

Dec 8, 2005

Appl. No.:

11/299080

Inventors:

Ashfaq R. Shaikh - San Jose CA, US
Chang Hee Hong - Pleasanton CA, US
Ting-Sheng Ku - San Jose CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

H03K 19/0175
H03K 19/094

US Classification:

326 81, 326 68, 327309

Abstract:

Techniques and circuits for ensuring one or more circuit components are not subjected to voltage levels above their rated voltage tolerance due to core logic and I/O logic supply voltages reaching final voltage levels at different times are provided. According to some embodiments, an internal voltage supply sense circuit may monitor a level of a voltage supply that powers core logic that generates control signals used to program a voltage regulator. In response to determining the core logic voltage supply is below a predetermined level, the sense circuit may generate one or more regulated voltage signals to override regulated voltage signals generated by the voltage regulator.

US Patent:

7755402, Jul 13, 2010

Filed:

Apr 28, 2006

Appl. No.:

11/413294

Inventors:

Ting-Sheng Ku - San Jose CA, US
Ashfaq R. Shaikh - San Jose CA, US

Assignee:

nVidia - Santa Clara CA

International Classification:

H03L 7/00

US Classification:

327153, 327 12, 327161, 327261

Abstract:

Embodiments for positioning rising and/or filling edges of data strobe signals are disclosed. One example embodiment may comprise receiving a data signal, positioning an edge of a first delayed data strobe signal associated with the data signal by a first programmable amount, and positioning an edge of a second delayed data strobe signal associated with the data signal by a second programmable amount, wherein the second delayed data strobe signal is shifted approximately one bit-time in relation to the first delayed data strobe signal.