Ashish S Gupta

US Patent:

7249273, Jul 24, 2007

Filed:

Jun 23, 2003

Appl. No.:

10/601502

Inventors:

Chengting Zhao - Chandler AZ, US
Ashish Gupta - San Jose CA, US
Edward R. Helder - Fremont CA, US
Fangxing Wei - Gilbert AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04L 7/00

US Classification:

713400

Abstract:

Some embodiments provide a synchronization circuit to receive a synchronization signal, the synchronization signal substantially synchronized with a data transition, to synchronize the synchronization signal with a clock signal, and to generate a load signal based on the synchronized synchronization signal. Also provided may be a ring counter to receive the load signal from the synchronization circuit and to circularly propagate the load signal.

US Patent:

7739876, Jun 22, 2010

Filed:

Dec 27, 2006

Appl. No.:

11/616794

Inventors:

Ashish Gupta - Chandler AZ, US
David S. Chau - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

F25B 21/02

US Classification:

62 32, 62 37, 622592

Abstract:

An apparatus including a socket having a socket body and a cavity within the socket body. The apparatus further including a thermoelectric cooler coupled to an in-substrate voltage regulator positioned within the cavity. A method including coupling a thermoelectric cooler to an in-substrate voltage regulator positioned within a cavity of a socket and electrically coupling the thermoelectric cooler to the socket using a contact of the socket. A system including an electronic appliance having a processor including an in-substrate voltage regulator positioned within a cavity of a socket coupled to the processor. The system further including a thermoelectric cooler positioned within the cavity and coupled to the in-substrate voltage regulator.

US Patent:

7742299, Jun 22, 2010

Filed:

May 9, 2008

Appl. No.:

12/118338

Inventors:

Ioan Sauciuc - Phoenix AZ, US
Sandeep Ahuja - Santa Clara CA, US
Ashish Gupta - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H05K 7/20

US Classification:

361695, 361694, 361719, 361720, 174 161

Abstract:

A cooling system including one or more piezo fans for an electronic assembly is disclosed. The electronic assembly may include heat-generating components coupled with a front side of a printed circuit board (PCB) and one or more piezo fans coupled with a back side of the PCB. One or more piezo fans may be capable of cooling the heat-generating components from the back side. The cooling system may further include a heat sink coupled with the back side of the PCB.

US Patent:

7982478, Jul 19, 2011

Filed:

Dec 29, 2008

Appl. No.:

12/345234

Inventors:

Nader Abazarnia - Chandler AZ, US
Ashish X Gupta - Chandler AZ, US
Suzana Prstic - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G01R 31/26

US Classification:

32475404

Abstract:

In some embodiments, a liquid TIM dispense and removal method and assembly is presented. In this regard, a method is introduced including loading an absorbent material of a thermal control unit with a liquid thermal interface material (TIM), pressing the absorbent material against an integrated circuit device causing the liquid TIM to be released, testing the integrated circuit device, and removing the absorbent material from against the integrated circuit device causing the liquid TIM to be reabsorbed. Other embodiments are also disclosed and claimed.

US Patent:

8410802, Apr 2, 2013

Filed:

Dec 24, 2009

Appl. No.:

12/647261

Inventors:

Ashish Gupta - Chandler AZ, US
James R. Hastings - Chandler AZ, US
Nader N. Abazarnia - Chandler AZ, US
Suzana Prstic - Chandler AZ, US
Jerome L. Garcia - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G01R 31/00

US Classification:

32475003, 32475001

Abstract:

Systems and methods including testing of electronic components are described. One system relates to a system including a thermal control unit adapted to control the temperature of at least a portion of an electronic component during testing. The system includes at least one conduit extending through a portion of the thermal control unit, the conduit sized to permit the flow of a thermal interface material therethrough, the thermal interface material comprising a liquid. The at least one conduit is positioned so that the thermal interface material can be delivered through the conduit and onto the electronic component. The system also includes a device adapted to control the flow of the thermal interface material through the conduit, wherein the flow can be controlled to deliver the thermal interface material to the electronic component and to remove the thermal interface material from the electronic component. Other embodiments are described and claimed.

US Patent:

20080002365, Jan 3, 2008

Filed:

Jun 29, 2006

Appl. No.:

11/479632

Inventors:

Ashish Gupta - Chandler AZ, US

International Classification:

H05K 7/20

US Classification:

361700

Abstract:

In some embodiments, socket enabled cooling of in-substrate voltage regulator is presented. In this regard, a socket is introduced having a socket body with a substantially central cavity, a plurality of contacts through the socket body arranged in a substantially square pattern around the cavity, and an integrated heat spreader substantially covering the cavity. Other embodiments are also disclosed and claimed.

US Patent:

20080237843, Oct 2, 2008

Filed:

Mar 27, 2007

Appl. No.:

11/729079

Inventors:

Ashish Gupta - Chandler AZ, US
Leonel R. Arana - Phoenix AZ, US
David Song - Chandler AZ, US
Chia-Pin Chiu - Tempe AZ, US
Ravi Prasher - Mesa AZ, US
Chris Matayabas - Chandler AZ, US
Nirupama Chakrapani - Chandler AZ, US

International Classification:

H01L 23/367
H01L 21/58

US Classification:

257713, 438122, 257E23104, 257E21499

Abstract:

A microelectronic package. The package includes a substrate; a die mounted onto the substrate; an integrated heat spreader mounted onto the substrate, and thermally coupled to a backside of the die; and a sealant material bonding the integrated heat spreader to the substrate, the sealant material having a bulk thermal conductivity above about 1 W/m/ C. and a modulus of elasticity lower than a modulus of elasticity of solder.

US Patent:

20090166890, Jul 2, 2009

Filed:

Dec 31, 2007

Appl. No.:

12/006286

Inventors:

Gregory M. Chrysler - Sun Lakes AZ, US
Ashish Gupta - Chandler AZ, US

International Classification:

H01L 23/48
H01L 21/02

US Classification:

257778, 438108, 257E23172, 257E21002

Abstract:

A flip-chip package is described. The package has an integrated circuit (IC) die positioned within an epoxy layer on the top surface of a package substrate. Cooling of the IC die is facilitated by a heat spreader having two contact surfaces separated by a pedestal, the first contact surface for attachment to the epoxy layer the second contact surface for thermal attachment to the exposed backside surface of the IC die, the pedestal thickness is selected so as to create a gap between the first contact surface and the epoxy layer.