Ashish Te Gupta

US Patent:

6598191, Jul 22, 2003

Filed:

Nov 23, 1999

Appl. No.:

09/444610

Inventors:

Debendra Das Sharma - Santa Clara CA
Ashish Gupta - Cupertino CA
Donald A. Williamson - Cupertino CA

Assignee:

Hewlett-Packard Development Companay, L.P. - Houston TX

International Classification:

G01R 313177

US Classification:

714726, 703 15, 714724, 714731, 714741, 714744

Abstract:

A function for verifying an asynchronous boundary behavior of a digital system. The asynchronous boundary is formed at a coupling between a first series of registers clocked by a write clock (the write domain), and a second series of registers clocked by a read clock (the read domain). A delay register and multiplexer are inserted after a predetermined register within the digital system, where the predetermined register and delay register are clocked by the same clock. The output of the predetermined register is coupled to both the first input of multiplexer and a first input of the delay register. The delay register is coupled to the second input of the multiplexer. A selector is coupled to the multiplexer for selecting which of the two multiplexer inputs to pass to subsequent registers in the digital system. By inserting the delay register/multiplexer at or after the asynchronous boundary, any signal level uncertainty present between the read domain and the write domain is captured and propagated through the digital system.

US Patent:

6611936, Aug 26, 2003

Filed:

Apr 28, 2000

Appl. No.:

09/560191

Inventors:

Darren S. Jue - Sunnyvale CA
Ashish Gupta - Cupertino CA

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G01R 3128

US Classification:

714741, 714 33, 703 14, 703 28, 716 4

Abstract:

A method and apparatus are disclosed for verifying the functional design of a systems response to propagation delays from the inputs of source synchronous links during testing. The system emulates propagation delays by receiving data slice from a source, applying a random or known delay to the data slice, and sending the delayed data slice to the chip under test. In one embodiment, multiple data slices having varying delay values may be used to test combinations of delays. A programmable delay. element is used to emulate the propagation delays. This is may be implemented at the hardware description level by receiving the data slice onto multiple data buses, applying a different delay to the data slice on each data bus, and sending the delayed data slices as inputs into a multiplexor. The multiplexor may have a selector input that determines which amount of delay to test. Alternatively, the delay may be emulated using a higher level programming language and creating a multidimensional array.

US Patent:

6807603, Oct 19, 2004

Filed:

Feb 22, 2002

Appl. No.:

10/080739

Inventors:

Ashish Gupta - San Jose CA
Debendra Das Sharma - Santa Clara CA

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1208

US Classification:

711 5, 711157, 711206, 711207, 711208

Abstract:

A method of accessing a plurality of memories and a plurality of input/output modules includes providing at least one map table, including a plurality of entries. Each entry includes an entry type identifier and a plurality of entry items. A first logical address including a plurality of address bits is received. An entry in the at least one map table is identified based on a first set of the address bits. A type of the identified entry is determined based on the entry type identifier of the identified entry. An entry item in the identified entry is identified based on a second set of the address bits if the entry type identifier indicates an input/output type entry. An entry item in the identified entry is identified based on a third set of the address bits if the entry type identifier indicates a memory type entry.

US Patent:

6832270, Dec 14, 2004

Filed:

Mar 8, 2002

Appl. No.:

10/092603

Inventors:

Debendra Das Sharma - Santa Clara CA
Ashish Gupta - San Jose CA

Assignee:

Hewlett-Packard Development Company, L.P. - Fort Collins CO

International Classification:

G06F 300

US Classification:

710 15, 710 19, 714 3, 370228

Abstract:

A virtual input/output (I/O) interconnect mechanism, and a corresponding method, for use in a computer system having a plurality of I/O devices and a plurality of processing units, where I/O devices and processing units are coupled by one or more bridge units, includes an address decode block having a multiplexer that multiplexes inputs to produce an address, where the address relates to a transaction related to a processor unit, a range register decoder that receives the address and provides a destination address of a module to receive the transaction related to the address, and a reroute module identification block that receives the destination address. The reroute module identification block, includes an original module identification that provides an address of one or more original modules in the computer system, and a remapped module identification that provides logical destination module identifications of substitute modules in the computer system, where a substitute module replaces functions of an original module in the computer system.

US Patent:

6874070, Mar 29, 2005

Filed:

Feb 22, 2002

Appl. No.:

10/080440

Inventors:

Ashish Gupta - San Jose CA, US
William R. Bryg - Saratoga CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F012/00

US Classification:

711157, 711205, 711 5, 711209

Abstract:

A method of accessing a plurality of memories in an interleaved manner using a contiguous logical address space includes providing at least one map table. The at least one map table includes a plurality of entries. Each entry includes a plurality of entry items. Each entry item identifies one of the memories. A first logical address is received. The first logical address includes a plurality of address bits. The plurality of address bits includes a first set of address bits corresponding to a first set of entries in the at least one map table. A first entry in the first set of entries is identified based on the first set and a second set of the address bits. A first entry item in the first entry is identified based on a third set of the address bits. The memory identified by the first entry item is accessed.

US Patent:

6889250, May 3, 2005

Filed:

Mar 1, 2001

Appl. No.:

09/797503

Inventors:

Jeffrey P. Bezos - Greater Seattle WA, US
Ashish Gupta - Los Altos CA, US

Assignee:

Amazon.com, Inc. - Seattle WA

International Classification:

G06F013/00

US Classification:

709218, 709203, 709204, 709217, 709219

Abstract:

A method and system for allowing users of different web pages to exchange information. The information exchange system identifies groups of related web pages and maintains a database of user-supplied information for each group of related web pages. When a user accesses a web page, the information exchange often displays in a separate area the information associated with the group of related web pages. Also, the information exchange system allows the user to enter information that will be displayed to other users who access related web pages.

US Patent:

7103728, Sep 5, 2006

Filed:

Jul 23, 2002

Appl. No.:

10/201180

Inventors:

Debendra Das Sharma - Santa Clara CA, US
Ashish Gupta - Cupertino CA, US
William R. Bryg - Saratoga CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 12/00

US Classification:

711154, 711141, 711147, 711148, 711153, 711156, 711161, 711162

Abstract:

A distributed-memory multi-processor system includes a plurality of cells communicatively coupled to each other and collectively including a plurality of processors, caches, main memories, and cell controllers. Each of the cells includes at least one of the processors, at least one of the caches, one of the main memories, and one of the cell controllers. Each of the cells is configured to perform memory migration functions for migrating memory from a first one of the main memories to a second one of the main memories in a manner that is invisible to an operating system of the system.

US Patent:

7328375, Feb 5, 2008

Filed:

Dec 30, 2003

Appl. No.:

10/749660

Inventors:

Ashish Gupta - San Jose CA, US
Bahaa Fahim - Sunnyvale CA, US
Kent Dickey - Westford MA, US
Jonathan Jasper - San Jose CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 11/00

US Classification:

714 45, 714 30, 714 31

Abstract:

An example computer system includes a first bridge device that includes an interface controller. The interface controller combines debug information generated within the bridge device with a training pattern. The first bridge device is coupled to a second bridge device via a high-speed asynchronous interconnect. The first bridge device converts the debug information and training pattern into a packet to be transmitted over the interconnect to the second bridge device. The training pattern serves to allow the second bridge device to maintain bit and symbol synchronization during the transfer; of the debug information.