Ashok K Krishnamurthi

age ~59

from Saratoga, CA

Also known as:
  • Ashok Krishnamurth
  • Ashok Iyengar
  • Ashok I
Phone and address:
14200 Shady Oak Ct, Saratoga, CA 95070
4087172340

Ashok Krishnamurthi Phones & Addresses

  • 14200 Shady Oak Ct, Saratoga, CA 95070 • 4087172340
  • Shady Oak Ct, Saratoga, CA 95070
  • Carmel, CA
  • 3231 Fieldgate Ct, San Jose, CA 95148 • 4082239958
  • Sunnyvale, CA
  • Santa Clara, CA
  • Cupertino, CA
  • 14200 Shady Oak Ct, Saratoga, CA 95070

Work

  • Company:
    Xsigo systems
    Aug 2004
  • Position:
    Chairman and chief executive officer

Education

  • Degree:
    Graduate or professional degree

Skills

Sales

Emails

Industries

Computer Networking

Vehicle Records

  • Ashok Krishnamurthi

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  • Address:
    14200 Shady Oak Ct, Saratoga, CA 95070
  • Phone:
    4088722463
  • VIN:
    WDDNG71X07A048159
  • Make:
    MERCEDES-BENZ
  • Model:
    S-CLASS
  • Year:
    2007

Us Patents

  • Traceless Midplane

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  • US Patent:
    6538899, Mar 25, 2003
  • Filed:
    Jan 2, 2001
  • Appl. No.:
    09/751838
  • Inventors:
    Ashok Krishnamurthi - San Jose CA
    Ramalingam K. Anand - San Jose CA
  • Assignee:
    Juniper Networks, Inc. - Sunnyvale CA
  • International Classification:
    H01R 1216
  • US Classification:
    361788, 361791, 361792, 361803, 439 61
  • Abstract:
    A traceless midplane contains substantially no traces, pins, or active components and includes a front portion and a back portion. The front portion includes first connectors. The back portion includes second connectors arranged in a grid pattern. Each of the second connectors includes electrically-conductive conduits that connect the second connector to a corresponding one of the first connectors through the midplane. The second connectors include data connection points, ground connection points, and clock connection points. At least some of the data connection points are separated from each other and from the clock connection points by the ground connection points.
  • Reset Control For Systems Using Programmable Logic

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  • US Patent:
    6578186, Jun 10, 2003
  • Filed:
    Dec 22, 2000
  • Appl. No.:
    09/742538
  • Inventors:
    Michael Armstrong - Sunnyvale CA
    Ashok Krishnamurthi - San Jose CA
  • Assignee:
    Juniper Networks - Sunnyvale CA
  • International Classification:
    G06F 1750
  • US Classification:
    716 16, 326 38, 716 17
  • Abstract:
    A system prevents processor faults during the configuring of a programmable device. The system sets the processor into a reset mode, configures the programmable device using first configuration data, and determines whether the configuring using the first configuration data is successful. When the programmable device is not successfully configured, the system configures the programmable device using second configuration data and determines whether the configuring using the second configuration data is successful. The system releases the processor from the reset mode when the programmable device is successfully configured using the first or second configuration data or when the configuration of the programmable device using the second configuration data fails.
  • Diagnostic Access To Processors In A Complex Electrical System

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  • US Patent:
    6826713, Nov 30, 2004
  • Filed:
    Jan 2, 2001
  • Appl. No.:
    09/751937
  • Inventors:
    Michael Beesley - Hillsborough CA
    Ross Heitkamp - Mountain View CA
    Ashok Krishnamurthi - San Jose CA
    Kenneth Richard Powell - Palo Alto CA
  • Assignee:
    Juniper Networks, Inc. - Sunnyvale CA
  • International Classification:
    G06F 1100
  • US Classification:
    714 25, 714 48, 713 2
  • Abstract:
    A debugging and diagnostic system allows a developer to receive low-level diagnostic information from multiple processors in a complex electrical system. A bus connects a master processor to the processors to be debugged via corresponding receiver/driver circuits. The receiver/driver circuits receive serial information from the processors and transmit it to the bus. The master processor controls the receiver/driver circuits through a control logic circuit.
  • Reliable And Redundant Control Signals In A Multi-Master System

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  • US Patent:
    6970961, Nov 29, 2005
  • Filed:
    Jan 2, 2001
  • Appl. No.:
    09/751841
  • Inventors:
    Ross Heitkamp - Mountain View CA, US
    Michael Armstrong - Sunnyvale CA, US
    Michael Beesley - Hillsborough CA, US
    Ashok Krishnamurthi - San Jose CA, US
    Kenneth Richard Powell - Palo Alto CA, US
  • Assignee:
    Juniper Networks, Inc. - Sunnyvale CA
  • International Classification:
    G06F013/00
    G06F011/00
  • US Classification:
    710110, 714 11
  • Abstract:
    A network device includes redundant buses, redundant master controllers, and slave controllers. Each of the master controllers connects to a corresponding one of the buses. One of the master controllers acts as an active master and the other master controllers act as standby masters. The active master commences a bus cycle that includes an address interval and a data interval, provides a destination address on the corresponding bus during the address interval, and transmits or receives a command or data during the data interval. The slave controllers connect to the bus, detect commencement of the bus cycle, sample the destination address from the bus a predetermined amount of time after commencement of the address interval, and transmit or receive a command or data during the data interval.
  • Multi-Master And Diverse Serial Bus In A Complex Electrical System

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  • US Patent:
    6981087, Dec 27, 2005
  • Filed:
    Jan 2, 2001
  • Appl. No.:
    09/751449
  • Inventors:
    Ross Heitkamp - Mountain View CA, US
    Michael Armstrong - Sunnyvale CA, US
    Michael Beesley - Hillsborough CA, US
    Ashok Krishnamurthi - San Jose CA, US
    Kenneth Richard Powell - Palo Alto CA, US
    Mike M. Wu - Fremont CA, US
  • Assignee:
    Juniper Networks, Inc. - Sunnyvale CA
  • International Classification:
    G06F013/00
    G06F013/14
    G06F013/368
  • US Classification:
    710301, 710300, 710305, 710119
  • Abstract:
    A two wire serial bus is connected between different circuit boards in a complex electrical system. The two wire serial bus may be used to receive status information about each of the circuit boards in the system. A master control processor on one of the circuit boards controls which of the other circuit boards are active on the serial bus. Each of the non-master circuit boards includes a series of switches that electrically isolate or connect portions of the two wire serial bus from one another. Through the series of switches, both the master control processor and processors local to each of the other circuit boards may simultaneously access different portions of the serial bus.
  • Systems And Methods For Allocating Bandwidth For Processing Of Packets

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  • US Patent:
    7016367, Mar 21, 2006
  • Filed:
    Jan 2, 2001
  • Appl. No.:
    09/751454
  • Inventors:
    Stefan Dyckerhoff - Palo Alto CA, US
    Pankaj Patel - Cupertino CA, US
    Pradeep Sindhu - Los Altos Hills CA, US
    Ashok Krishnamurthi - San Jose CA, US
    Ramalingam K. Anand - San Jose CA, US
    Dennis C. Ferguson - Mountain View CA, US
    Chang-Hong Wu - Cupertino CA, US
  • Assignee:
    Juniper Networks, Inc. - Sunnyvale CA
  • International Classification:
    H04L 12/54
  • US Classification:
    370429, 709105
  • Abstract:
    A network device includes one or more sprayers, multiple packet processors, and one or more desprayers. The sprayers receive packets on at least one incoming packet stream and distribute the packets according to a load balancing scheme that balances the number of bytes of packet data that is given to each of the packet processors. The packet processors receive the packets from the sprayers and process the packets to determine routing information for the packets. The desprayers receive the processed packets from the packet processors and transmit the packets on at least one outgoing packet stream based on the routing information.
  • Bandwidth Division For Packet Processing

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  • US Patent:
    7139282, Nov 21, 2006
  • Filed:
    Mar 24, 2000
  • Appl. No.:
    09/534838
  • Inventors:
    Stefan Dyckerhoff - Palo Alto CA, US
    Pankaj Patel - Cupertino CA, US
    Pradeep Sindhu - Mountain View CA, US
    Ashok Krishnamurthi - San Jose CA, US
    Ramalingam Krishnamurthi Anand - San Jose CA, US
  • Assignee:
    Juniper Networks, Inc. - Sunnyvale CA
  • International Classification:
    H04L 12/54
  • US Classification:
    370428, 370468
  • Abstract:
    A bandwidth divider and method for allocating bandwidth between a plurality of packet processors. The bandwidth divider includes a plurality of counters for measuring the bandwidth of data packets transferred from the bandwidth divider to a respective packet processor; and a controller for analyzing the plurality of counters and transferring a data packet to a selected packet processor based on the contents of the counters. The method monitors the bandwidth consumed by the packet processors; determines, based on the bandwidth consumed by the packet processors, which packet processor has consumed the least amount of bandwidth; and allocates a next data packet to the packet processor which has consumed the least amount of bandwidth.
  • High-Speed Line Interface For Networking Devices

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  • US Patent:
    7164698, Jan 16, 2007
  • Filed:
    Jan 3, 2001
  • Appl. No.:
    09/752827
  • Inventors:
    Ashok Krishnamurthi - San Jose CA, US
    Jeffrey Scott Dredge - San Jose CA, US
    Ramesh Padmanabhan - Los Altos CA, US
    Ramalingam K. Anand - San Jose CA, US
  • Assignee:
    Juniper Networks, Inc. - Sunnyvale CA
  • International Classification:
    H04J 3/02
  • US Classification:
    370541, 370539, 370545
  • Abstract:
    Systems and methods, consistent with the present invention, provide a high-speed line interface for networking devices. Such an interface may be used in networking devices, such as routers and switches, for receiving data from, and transmitting data to, high-speed links, such as those lines carrying data at rates of 2. 5 Gbit/sec, 10 Gbit/sec, and 40 Gbit/sec and more. In a preferred embodiment, the interface deserializes data from an incoming data stream onto a multi-line bus so that the data may be processed at a lower clock speed. Packets are extracted from the data on the multi-line bus and distributed among a plurality of switching/forwarding modules for processing.

Resumes

Ashok Krishnamurthi Photo 1

Chairman And Chief Executive Officer

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Location:
San Francisco, CA
Industry:
Computer Networking
Work:
Xsigo Systems
Chairman and Chief Executive Officer
Skills:
Sales
Name / Title
Company / Classification
Phones & Addresses
Ashok Krishnamurthi
Renoo, LLC
Music Development & Sales
1249 Acadia Ave, Milpitas, CA 95035

Wikipedia

Xsigo Systems

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Xsigo Systems was founded in August 2004 by three brothers: Ashok Krishnamurthi, R.K. Anand and S.K. Vinod. and Shreyas Shah. The privately held company is ...

Youtube

Dr. Ashok Krishnamoorthy - Make an Impact on ...

In Richmond, we pride ourselves on making our services accessible and ...

  • Duration:
    1m 3s

Xsigo Data Center Fabric Technology

Xsigo Founder Ashok Krishnamurthi discusses Xsigo Data Center Fabric a...

  • Duration:
    2m 16s

Papanasam Ashok Ramani - Vocal | Mahavidwan C...

Mahavidwan Culcutta K. S. Krishnamurthi Centenary Year Celebration | C...

  • Duration:
    1h 58m 7s

Ashok's Bellarmine Speech

  • Duration:
    2m 13s

Krish Ashok | The Tale of a Curry: A 2.7 Bill...

Krish Ashok discusses his book "Masala Lab: The Science of Indian Cook...

  • Duration:
    1h 1m 55s

Krishnamurthi Garintlo || Telugu Short Film 2...

Krishnamurthi Garintlo Telugu Short Film 2016 Cast : Manoj krishna tan...

  • Duration:
    38m 34s

Facebook

Ashok Krishnamurthi Photo 2

Ashok Krishnamurthi

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Friends:
Pravin Kumar, Ramesh Balasubramanian, Nilesh Aurangabadkar, Bhuvana Ramakrishnan

Googleplus

Ashok Krishnamurthi Photo 3

Ashok Krishnamurthi


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