Benjamin C Brown

US Patent:

53217020, Jun 14, 1994

Filed:

Feb 9, 1993

Appl. No.:

8/015557

Inventors:

Benjamin J. Brown - Westlake Village CA
Peter A. Reichert - Newbury Park CA

Assignee:

Teradyne, Inc. - Boston MA

International Classification:

G06F 1100

US Classification:

371 27

Abstract:

A high speed timing generator including a pattern generator circuit, a plurality local generator circuits associated with respective nodes of a device under test, and a plurality of distribution paths. The pattern generator circuit has a high speed pattern generator which generates a high speed address and a divider circuit which divides the high speed address into a plurality of lower speed address patterns at a lower frequency. Each local generator circuit having a plurality of signal generator circuits which operate at the lower frequency of the lower speed address patterns and provide lower frequency signals and a high speed formatter circuit which uses the lower frequency signals to provide a high frequency signal. The plurality of distribution paths provide the lower speed address patterns to the local generator circuit.

US Patent:

52804860, Jan 18, 1994

Filed:

Feb 8, 1993

Appl. No.:

8/015070

Inventors:

Brian J. Arkin - Simi Valley CA
Benjamin J. Brown - Westlake Village CA
Peter A. Reichert - Newbury Park CA

Assignee:

Teradyne, Inc. - Boston MA

International Classification:

G01R 3128

US Classification:

371 291

Abstract:

An apparatus for processing failure information received from a node of a circuit under test. The apparatus includes a fail processor which receives test data from a node and generates failure data based upon the test data, a plurality of fail memories, each memory being configured to receive and store certain fail data, and a sequence memory configured-to store sequence information indicating in what order the failure data is stored in the plurality of fail memories.

US Patent:

55703836, Oct 29, 1996

Filed:

Aug 15, 1994

Appl. No.:

8/290477

Inventors:

Benjamin J. Brown - Westlake Village CA
Peter A. Reichert - Thousand Oaks CA

Assignee:

Teradyne, Inc. - Boston MA

International Classification:

G06F 1100

US Classification:

371 62

Abstract:

Apparatus and method for detecting timing hazards which might be introduced in a pattern for execution on a tester when edges are improperly programmed in the pattern. The apparatus includes hazard detection circuits associated with the pins of the tester. Each circuit receives control inputs which specify which edges are involved in the hazard and limits on the permissible time between the specified edges. In operation, the pattern is executed repeatedly, once for each hazard which must be detected. The programmed times for the selected edge as well as the drive and format for each period of the pattern are variable inputs to the circuit.

US Patent:

52705820, Dec 14, 1993

Filed:

Feb 9, 1993

Appl. No.:

8/015403

Inventors:

Benjamin J. Brown - Westlake Village CA
Peter A. Reichert - Newbury Park CA

Assignee:

Teradyne, Inc. - Boston MA

International Classification:

H03K 513
H03K 1726

US Classification:

307269

Abstract:

"The present invention provides an interpolator circuit including a register, a pulse swallower, a ramping circuit and a compare circuit. The interpolator may be employed in a high speed timing generator".

US Patent:

62861204, Sep 4, 2001

Filed:

Sep 1, 1994

Appl. No.:

8/299753

Inventors:

Peter A. Reichert - Thousand Oaks CA
Benjamin J. Brown - Westlake Village CA

Assignee:

Teradyne, Inc. - Boston MA

International Classification:

G06F 1100

US Classification:

714738

Abstract:

A tester having a fast but flexible pattern generator which is implemented using readily available memories. The tester includes a pattern memory which holds test vectors. The vectors are organized into modules. The order of execution of the modules is selected from a list stored in memory. In the preferred embodiment, memories which operate in burst mode are used to implement the pattern memory. To compensate for the decrease in data rate which occurs when execution switches between modules in the middle of a burst, the memory refresh rate is dynamically altered upon switching between modules.

US Patent:

53217004, Jun 14, 1994

Filed:

Oct 30, 1990

Appl. No.:

7/605977

Inventors:

Benjamin J. Brown - Westlake Village CA
Peter A. Reichert - Newbury Park CA

Assignee:

Teradyne, Inc. - Boston MA

International Classification:

G06F 1100
G01R 3128

US Classification:

371 27

Abstract:

A high speed timing generator including a pattern generator circuit, a plurality local generator circuits associated with respective nodes of a device under test, and a plurality of distribution paths. The pattern generator circuit has a high speed pattern generator which generates a high speed address and a divider circuit which divides the high speed address into a plurality of lower speed address patterns at a lower frequency. Each local generator circuit has a plurality of signal generator circuits which operate at the lower frequency of the lower speed address patterns and provide lower frequency signals and a high speed formatter circuit which uses the lower frequency signals to provide a high frequency signal. The plurality of distribution paths provide the lower speed address patterns to the local generator circuit.