Benjamin Te Cho

US Patent:

20180018104, Jan 18, 2018

Filed:

Jul 15, 2016

Appl. No.:

15/211488

Inventors:

- Sunnyvale CA, US
Benjamin Y. Cho - Sunnyvale CA, US
Nuwan Jayasena - Sunnyvale CA, US

International Classification:

G06F 3/06
G11C 13/00

Abstract:

Methods and apparatus of dynamically determining a variable reset latency time based on a data pattern of the data to be written into memory is disclosed. A memory controller determines a variable reset latency time for a plurality of memory cells depending on the bit values to be written into the plurality of memory cells in response to a write request having corresponding bit values. A write latency for the plurality of memory cells is dependent on the bit values being written into the plurality of memory cells. The memory controller writes the bit values of the write request to the plurality of memory cells within the determined variable reset latency time.