Benjamin A Eldridge

US Patent:

6339338, Jan 15, 2002

Filed:

Jan 18, 2000

Appl. No.:

09/484600

Inventors:

Benjamin N. Eldridge - Danville CA
Charles A. Miller - Fremont CA

Assignee:

Formfactor, Inc. - Livermore CA

International Classification:

G01R 3126

US Classification:

324765, 324764, 307 43

Abstract:

A main power supply continuously provides a current to a power input terminal of an integrated circuit device under test (DUT). The DUTs demand for current at the power input terminal temporarily increases during state changes in synchronous logic circuits implemented within the DUT. To limit variation (noise) in voltage at the power input terminal arising from these temporary increases in current demand, a charged capacitor is connected to the power input terminal during each DUT state change. The capacitor discharges into the power input terminal to supply additional current to meet the DUTs increased demand. Following each DUT state change the capacitor is disconnected from the power input terminal and charged to a level sufficient to meet a predicted increase in current demand during a next DUT state change.

US Patent:

6429029, Aug 6, 2002

Filed:

Dec 31, 1998

Appl. No.:

09/224166

Inventors:

Benjamin N. Eldridge - Danville CA
Igor Y. Khandros - Orinda CA
David V. Pedersen - Scotts Valley CA
Ralph G. Whitten - San Jose CA

Assignee:

FormFactor, Inc. - Livermore CA

International Classification:

H01L 2166

US Classification:

438 14, 438 10, 438 17

Abstract:

One embodiment of the present invention concerns a design methodology for generating a test die for a product die including the step of concurrently designing test circuitry and a product circuitry in a unified design. The test circuitry can be designed to provide a high degree of fault coverage for the corresponding product circuitry generally without regard to the amount of silicon area that will be required by the test circuitry. The design methodology then partitions the unified design into the test die and the product die. The test die includes the test circuitry and the product die includes the product circuitry. The product and test die may then be fabricated on separate semiconductor wafers. By partitioning the product circuitry and test circuitry into separate die, embedded test circuitry can be either eliminated or minimized on the product die. This will tend to decrease the size of the product die and decrease the cost of manufacturing the product die while maintaining a high degree of test coverage of the product circuits within the product die.

US Patent:

6441315, Aug 27, 2002

Filed:

Nov 10, 1998

Appl. No.:

09/189761

Inventors:

Benjamin N. Eldridge - Danville CA
Gary W. Grube - Pleasanton CA
Igor Y. Khandros - Orinda CA
Alec Madsen - San Francisco CA
Gaetan L. Mathieu - Livermore CA

Assignee:

FormFactor, Inc. - Livermore CA

International Classification:

H05K 116

US Classification:

174260, 174267, 438117

Abstract:

An apparatus providing improved interconnection elements and tip structures for effecting pressure connections between terminals of electronic components is described. The tip structure of the present invention has a sharpened blade oriented on the upper surface of the tip structure such that the length of the blade is substantially parallel to the direction of horizontal movement of the tip structure as the tip structure deflects across the terminal of an electronic component. In this manner, the sharpened substantially parallel oriented blade slices cleanly through any non-conductive layer(s) on the surface of the terminal and provides a reliable electrical connection between the interconnection element and the terminal of the electrical component.

US Patent:

6456099, Sep 24, 2002

Filed:

Dec 31, 1998

Appl. No.:

09/224169

Inventors:

Benjamin N. Eldridge - Danville CA
Igor Y. Khandros - Orinda CA
David V. Pedersen - Scotts Valley CA
Ralph G. Whitten - San Jose CA

Assignee:

FormFactor, Inc. - Livermore CA

International Classification:

G01R 3102

US Classification:

324754, 3241581

Abstract:

One embodiment of the present invention concerns an integrated circuit that includes bond pads and special contact pads or points. The bond pads are for interfacing the integrated circuit as a whole with an external circuit, and are to be bonded to a package or circuit board. The bond pads are disposed on the die in a predetermined alignment such as a peripheral, grid, or lead-on-center alignment. The special contact pads are used to provide external test patterns to internal circuits and/or to externally monitor results from testing the internal circuits. The special contact pads may be advantageously located on the integrated circuit with a high degree of positional freedom. For one embodiment, the special contact pads may be disposed on the die at a location that is not in the same alignment as the bond pads. The special contact pads may be smaller than the bond pads so as not to increase the die size due to the special contact pads. The special contact points may also be used to externally program internal circuits (e. g.

US Patent:

6456103, Sep 24, 2002

Filed:

Oct 30, 2001

Appl. No.:

10/003596

Inventors:

Benjamin N. Eldridge - Danville CA
Charles A. Miller - Fremont CA

Assignee:

Formfactor, Inc. - Livermore CA

International Classification:

G01R 3126

US Classification:

324765, 3241581, 307 43

Abstract:

A main power supply continuously provides a current to a power input terminal of an integrated circuit device under test (DUT). The DUTs demand for current at the power input terminal temporarily increases during state changes in synchronous logic circuits implemented within the DUT. To limit variation (noise) in voltage at the power input terminal arising from these temporary increases in current demand, a charged capacitor is connected to the power input terminal during each DUT state change. The capacitor discharges into the power input terminal to supply additional current to meet the DUTs increased demand. Following each DUT state change the capacitor is disconnected from the power input terminal and charged to a level sufficient to meet a predicted increase in current demand during a next DUT state change.

US Patent:

6468098, Oct 22, 2002

Filed:

Aug 17, 1999

Appl. No.:

09/376759

Inventors:

Benjamin N. Eldridge - Danville CA

Assignee:

FormFactor, Inc. - Livermore CA

International Classification:

H01R 460

US Classification:

439197

Abstract:

An electrical interconnect assembly and methods for making an electrical interconnect assembly. In one embodiment, an interconnect assembly includes a flexible wiring layer having a plurality of first contact elements and a fluid containing structure which is coupled to the flexible wiring layer. The fluid, when contained in the fluid containing structure, presses the flexible wiring layer towards a device under test to form electrical interconnections between the first contact elements and corresponding second contact elements on the device under test. In a further embodiment, an interconnect assembly includes a flexible wiring layer having a plurality of first contact terminals and a semiconductor substrate which includes a plurality of second contact terminals. A plurality of freestanding, resilient contact elements, in one embodiment, are mechanically coupled to one of the flexible wiring layers or the semiconductor substrate and make electrical contacts between corresponding ones of the first contact terminals and the second contact terminals. In another embodiment, a method of making electrical interconnections includes joining a flexible wiring layer and a substrate together in proximity and causing a pressure differential between a first side and a second side of the flexible wiring layer.

US Patent:

6475822, Nov 5, 2002

Filed:

Dec 29, 2000

Appl. No.:

09/752853

Inventors:

Benjamin N. Eldridge - Danville CA
Gary W. Grube - Pleasanton CA
Igor Y. Khandros - Orinda CA
Gaetan L. Mathieu - Livermore CA

Assignee:

FormFactor, Inc. - Livermore CA

International Classification:

H01L 2144

US Classification:

438 52, 438 14, 438 15, 438117

Abstract:

Spring contact elements are fabricated by depositing at least one layer of metallic material into openings defined on a sacrificial substrate. The openings may be within the surface of the substrate, or in one or more layers deposited on the surface of the sacrificial substrate. Each spring contact element has a base end portion, a contact end portion, and a central body portion. The contact end portion is offset in the z-axis (at a different height) than the central body portion. The base end portion is preferably offset in an opposite direction along the z-axis from the central body portion. In this manner, a plurality of spring contact elements are fabricated in a prescribed spatial relationship with one another on the sacrificial substrate. The spring contact elements are suitably mounted by their base end portions to corresponding terminals on an electronic component, such as a space transformer or a semiconductor device, whereupon the sacrificial substrate is removed so that the contact ends of the spring contact elements extend above the surface of the electronic component. In an exemplary use, the spring contact elements are thereby disposed on a space transformer component of a probe card assembly so that their contact ends effect pressure connections to corresponding terminals on another electronic component, for the purpose of probing the electronic component.

US Patent:

6479308, Nov 12, 2002

Filed:

Dec 27, 2001

Appl. No.:

10/034608

Inventors:

Benjamin N. Eldridge - Danville CA

Assignee:

FormFactor, Inc. - Livermore CA

International Classification:

H01L 2166

US Classification:

438 14, 438132, 438 15

Abstract:

A method and system for sealing or covering exposed fuses on a semiconductor device are disclosed. A semiconductor device prober incorporating a spray device for applying a sealing compound to individual fuses on a semiconductor device subsequent to testing the semiconductor device is disclosed. A method and system for sealing exposed fuses on a semiconductor device is disclosed which allows the sealing step to be performed either prior to or following singulation of the semiconductor device into individual dice.