Benjamin Brian Eldridge

US Patent:

6476630, Nov 5, 2002

Filed:

May 9, 2000

Appl. No.:

09/568460

Inventors:

Ralph G. Whitten - San Jose CA
Benjamin N. Eldridge - Danville CA

Assignee:

FormFactor, Inc. - Livermore CA

International Classification:

G01R 3126

US Classification:

324765, 324763, 324754

Abstract:

Signal paths within an interconnect structure linking input/output (I/O) ports of an integrated circuit (IC) tester and test points of an IC die on a wafer are tested for continuity, shorts and resistance by using the interconnect structure to access a similar arrangement of test points on a reference wafer. Conductors in the reference wafer interconnect groups of test points. The tester may then test the continuity of signal paths through the interconnect structure by sending test signals between pairs of its ports through those signal paths and the interconnecting conductors within the reference wafer. A parametric test unit within the tester can also determine impedances of the signal paths through the interconnect structure by comparing magnitudes of voltage drops across pairs of its I/O ports to magnitudes of currents it transmits between the I/O port pairs.

US Patent:

6724209, Apr 20, 2004

Filed:

Apr 13, 2000

Appl. No.:

09/548885

Inventors:

Ralph G. Whitten - San Jose CA 95132
Benjamin N. Eldridge - Danville CA 94526

International Classification:

G01R 3102

US Classification:

324763, 324754, 3241381

Abstract:

Signal paths within an interconnect structure linking input/output (I/O) ports of an integrated circuit (IC) tester and test points of an IC die on a wafer are tested for continuity, shorts and resistance by using the interconnect structure to access a similar arrangement of test points on a reference wafer. Conductors in the reference wafer interconnect groups of test points. The tester may then test the continuity of signal paths through the interconnect structure by sending test signals between pairs of its ports through those signal paths and the interconnecting conductors within the reference wafer. A parametric test unit within the tester can also determine impedances of the signal paths through the interconnect structure by comparing magnitudes of voltage drops across pairs of its I/O ports to magnitudes of currents it transmits between the I/O port pairs.

US Patent:

7053637, May 30, 2006

Filed:

Jan 12, 2004

Appl. No.:

10/756477

Inventors:

Ralph G. Whitten - San Jose CA, US
Benjamin N. Eldridge - Danville CA, US

Assignee:

FormFactor, Inc. - Livermore CA

International Classification:

G01R 31/02

US Classification:

324754

Abstract:

Signal paths within an interconnect structure linking input/output (I/O) ports of an integrated circuit (IC) tester and test points of an IC die on a wafer are tested for continuity, shorts and resistance by using the interconnect structure to access a similar arrangement of test points on a reference wafer. Conductors in the reference wafer interconnect groups of test points. The tester may then test the continuity of signal paths through the interconnect structure by sending test signals between pairs of its ports through those signal paths and the interconnecting conductors within the reference wafer. A parametric test unit within the tester can also determine impedances of the signal paths through the interconnect structure by comparing magnitudes of voltage drops across pairs of its I/O ports to magnitudes of currents it transmits between the I/O port pairs.

US Patent:

7202677, Apr 10, 2007

Filed:

Dec 30, 2003

Appl. No.:

10/749028

Inventors:

David V. Pedersen - Scotts Valley CA, US
Benjamin N. Eldridge - Danville CA, US
Igor Y. Khandros - Orinda CA, US

Assignee:

FormFactor, Inc. - Livermore CA

International Classification:

G01R 31/02

US Classification:

324754

Abstract:

Products and assemblies are provided for socketably receiving elongate interconnection elements, such as spring contact elements, extending from electronic components, such as semiconductor devices. Socket substrates are provided with capture pads for receiving ends of elongate interconnection elements extending from electronic components. Various capture pad configurations are disclosed. Connections to external devices are provided via conductive traces adjacent the surface of the socket substrate. The socket substrate may be supported by a support substrate. In a particularly preferred embodiment the capture pads are formed directly on a primary substrate such as a printed circuit board.

US Patent:

7534654, May 19, 2009

Filed:

Apr 10, 2007

Appl. No.:

11/733562

Inventors:

David V. Pedersen - Scotts Valley CA, US
Benjamin N. Eldridge - Danville CA, US
Igor Y. Khandros - Orinda CA, US

Assignee:

FormFactor, Inc. - Livermore CA

International Classification:

H01L 21/44
H01L 21/48
H01L 21/50

US Classification:

438110, 438107, 438113, 257692, 257696, 324754, 324755

Abstract:

Products and assemblies are provided for socketably receiving elongate interconnection elements, such as spring contact elements, extending from electronic components, such as semiconductor devices. Socket substrates are provided with capture pads for receiving ends of elongate interconnection elements extending from electronic components. Various capture pad configurations are disclosed. Connections to external devices are provided via conductive traces adjacent the surface of the socket substrate. The socket substrate may be supported by a support substrate. In a particularly preferred embodiment the capture pads are formed directly on a primary substrate such as a printed circuit board.

US Patent:

20020004320, Jan 10, 2002

Filed:

Dec 4, 1998

Appl. No.:

09/205502

Inventors:

DAVID V. PEDERSEN - SCOTTS VALLEY CA, US
BENJAMIN N. ELDRIDGE - DANVILLE CA, US
IGOR Y. KHANDROS - ORINDA CA, US

International Classification:

H05K001/00

US Classification:

439/066000

Abstract:

Products and assemblies are provided for socketably receiving elongate interconnection elements, such as spring contact elements, extending from electronic components, such as semiconductor devices. Socket substrates are provided with capture pads for receiving ends of elongate interconnection elements extending from electronic components. Various capture pad configurations are disclosed. Connections to external devices are provided via conductive traces adjacent the surface of the socket substrate. The socket substrate may be supported by a support substrate. In a particularly preferred embodiment the capture pads are formed directly on a primary substrate such as a printed circuit board.