May 2012 to 2000 Director of Design Engineering/Chief Design EngineerMagSil Corp Santa Clara, CA Sep 2010 to May 2012 Design Manager/Sr. Design VerificationMicron Technology Inc San Jose, CA Feb 1998 to Dec 2009 Design ManagerMicron Technology Inc San Jose, CA Jun 2004 to Dec 2005 Design ManagerMicron Technology Inc San Jose, CA Jun 2000 to Jun 2004 Design Section ManagerMicron Technology Inc San Jose, CA Jun 1999 to Jun 2000 Senior Design EngineerMicron Technology Inc San Jose, CA Feb 1998 to Jun 1999 Senior Design EngineerXilinx Corp San Jose, CA 1996 to 1998 IC Design EngineerXilinx Corp San Jose, CA Jun 1994 to 1996 Product/Test EngineerIBM Almaden Research Center San Jose, CA Sep 1993 to 1994 Supplemental Research EngineerApplied Materials Santa Clara, CA Jun 1993 to Sep 1993 Manufacturing Engineer Intern
Education:
Santa Clara University Jun 1998 Masters of Science in Electrical EngineeringSanta Clara University Jun 1994 Bachelor of Science in Electrical Engineering
Christophe J. Chevallier - Mountain View CA Benjamin Louie - Sunnyvale CA
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 700
US Classification:
365201, 36518509
Abstract:
Memory devices having architectures permitting the application of a voltage differential across alternate bitlines facilitate identifying and locating shorts within the memory device with particular reference to flash memory devices. The memory devices include a first plurality of selective coupling devices coupled between a first plurality of bitlines and a first variable potential node. The memory devices further include a second plurality of selective coupling devices coupled between a second plurality of bitlines and a second variable potential node. The first plurality of selective coupling devices are responsive to a first control signal to selectively provide electrical communication between the first plurality of bitlines and the first variable potential node. The second plurality of selective coupling devices are responsive to a second control signal to selectively provide electrical communication between the second plurality of bitlines and the second variable potential node. Each variable potential node provides two or more potential states.
Column/Row Redundancy Architecture Using Latches Programmed From A Look Up Table
Vinod Lakhani - Palo Alto CA, US Benjamin Louie - Fremont CA, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 7/00
US Classification:
365200, 36523006, 36523003, 36518905, 36523008
Abstract:
A scheme for defective memory column or row substitution is disclosed which uses a programmable look-up table to store new addresses for column selection when certain column or row addresses are received. The new addresses are loaded into a programmable fuse latch each time an address transition is detected in the input address.
Vinod Lakhani - Palo Alto CA, US Benjamin Louie - Fremont CA, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 11/00
US Classification:
36518509, 365200, 36523001, 711103
Abstract:
An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended addressing allowing redundant erase blocks that are not utilized to repair general use erase blocks of the main memory array to be accessed and utilized as additional storage space by an end user. The additional storage space formed by the unused redundant erase blocks and the specified storage space of the main memory array is presented to the end user as a single contiguous address space. Additionally, the redundant erase blocks can be utilized to repair any damaged erase block in the memory array of the non-volatile erase block memory or Flash memory device regardless of bank placement.
Benjamin Louie - Fremont CA, US Yunqiu Wan - Mountain View CA, US Aaron Yip - Santa Clara CA, US Jin-Man Han - Santa Clara CA, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 7/10
US Classification:
36518905, 36523003
Abstract:
A non-volatile memory is described that utilizes a cache read mode of operation, where a next page of memory is being read/sensed from the memory array by the sense amplifiers while a previously read page of memory is being read from the memory I/O buffer, wherein the next page is user selected. This random cache read mode allows for a memory with a random page read capability, in which the address of the next page of data to be read is user selectable, which benefits from the low latency of a cache read mode of operation due to concurrent data sensing and data I/O.
Vinod Lakhani - Palo Alto CA, US Benjamin Louie - Fremont CA, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 11/00
US Classification:
36518509, 365200, 36523001, 711103
Abstract:
An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended addressing allowing redundant erase blocks that are not utilized to repair general use erase blocks of the main memory array to be accessed and utilized as additional storage space by an end user. The additional storage space formed by the unused redundant erase blocks and the specified storage space of the main memory array is presented to the end user as a single contiguous address space. Additionally, the redundant erase blocks can be utilized to repair any damaged erase block in the memory array of the non-volatile erase block memory or Flash memory device regardless of bank placement.
Vinod Lakhani - Palo Alto CA, US Benjamin Louie - Fremont CA, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 11/00
US Classification:
36518509, 365200, 36523001, 711103
Abstract:
An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended addressing allowing redundant erase blocks that are not utilized to repair general use erase blocks of the main memory array to be accessed and utilized as additional storage space by an end user. The additional storage space formed by the unused redundant erase blocks and the specified storage space of the main memory array is presented to the end user as a single contiguous address space. Additionally, the redundant erase blocks can be utilized to repair any damaged erase block in the memory array of the non-volatile erase block memory or Flash memory device regardless of bank placement.
Vinod Lakhani - Palo Alto CA, US Benjamin Louie - Fremont CA, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 11/00
US Classification:
36518509, 365200, 36523001, 711103
Abstract:
An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended addressing allowing redundant erase blocks that are not utilized to repair general use erase blocks of the main memory array to be accessed and utilized as additional storage space by an end user. The additional storage space formed by the unused redundant erase blocks and the specified storage space of the main memory array is presented to the end user as a single contiguous address space. Additionally, the redundant erase blocks can be utilized to repair any damaged erase block in the memory array of the non-volatile erase block memory or Flash memory device regardless of bank placement.
Vinod Lakhani - Palo Alto CA, US Benjamin Louie - Fremont CA, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G06F 11/00
US Classification:
714 8, 714710
Abstract:
A scheme for block substitution within a flash memory device is disclosed which uses a programmable look-up table to store new addresses for block selection when certain input block addresses are received. The new addresses are loaded into a programmable fuse latch each time an address transition is detected in the input address. The new addresses may contain block addresses or block and bank addresses.