Bernard L Morris

US Patent:

6396315, May 28, 2002

Filed:

May 3, 1999

Appl. No.:

09/304619

Inventors:

Bernard Lee Morris - Emmaus PA

Assignee:

Agere Systems Guardian Corp. - Berkeley Heights NJ

International Classification:

H03B 100

US Classification:

327112, 327321, 327108, 326 83, 326 14

Abstract:

A voltage clamp for a failsafe buffer used in connection with an electronic device. The voltage clamp clamps a voltage present at the output terminal of the buffer only when the electronic device is powered-on, and present a high impedance when the electronic device is not powered-on. Thus, when an electronic device such as a printer, for example, is connected to a network and the device is in a powered-on state, the voltage at the output terminal of the buffer is clamped to approximately the value of the electronic device power source. When the electronic device is powered-off, a voltage present at the output of the buffer will not clamped by the voltage clamp. Instead, the buffer will present a high impedance to the network and to other electronic devices connected thereto. Consequently, when an electronic device having a failsafe buffer constructed in accordance with the present invention enters an inoperable state due to device failure, power loss, etc. , yet remains physically connected to the network and to other electronic devices, the inoperable device will not affect operation of other devices connected to the network.

US Patent:

6433628, Aug 13, 2002

Filed:

May 17, 2001

Appl. No.:

09/859316

Inventors:

Bernard Lee Morris - Emmaus PA

Assignee:

Agere Systems Guardian Corp. - Orlando FL

International Classification:

H01L 2500

US Classification:

327565, 324765

Abstract:

A wafer testable integrated circuit (IC) and method for wafer testing the IC. The IC includes outside row buffer areas, inside row buffer areas having bi-directional buffers, routing circuitry between the buffer areas, and IC logic (including internal IC logic directly accessible through at least one inside row buffer area). The internal logic is indirectly accessible through outside row buffer areas via the routing circuitry coupled between the outside row buffer areas and the inside row buffer areas, and the bi-directional buffers of the inside row buffer areas. The method includes supplying a test signal to a first outside row buffer area, routing the test signal from the first outside row buffer area to internal logic accessible through one or more inside row buffer areas, applying the test signal to the internal logic to generate a resultant signal, routing the resultant signal to a second outside row buffer area, and interpreting the resultant signal at the second outside row buffer area.

US Patent:

6590433, Jul 8, 2003

Filed:

Dec 8, 2000

Appl. No.:

09/733445

Inventors:

James T. Clee - Orefield PA
Bernard L. Morris - Emmaus PA
James E. Guziak - Laurys Station PA

Assignee:

Agere Systems, Inc. - Allentown PA

International Classification:

H03B 100

US Classification:

327109, 327404, 327562, 326 83, 330257, 330288

Abstract:

A bi-directional buffer includes the capability to turn the current mirror off when the bi-directional buffer is in the receive mode and quickly turn the current mirror on when the bi-directional buffer goes into the transmit mode. This is accomplished in part by a pair of switches included in the current mirror, which are controlled by enable signals. The switches are configured such that the output transistor of the current mirror is turned on when the bi-directional buffer is in the transmit mode, and turned off when the bi-directional buffer is in the receive mode. Further, a pull up circuit may be added to the current mirror to more quickly bring the gate of the output transistor of the current mirror to its conduction threshold voltage.

US Patent:

6686789, Feb 3, 2004

Filed:

Mar 28, 2002

Appl. No.:

10/109245

Inventors:

Douglas D. Lopata - Boyertown PA
Bernard Lee Morris - Emmaus PA

Assignee:

Agere Systems, Inc. - Allentown PA

International Classification:

G05F 302

US Classification:

327334, 327546

Abstract:

A dynamic low power reference circuit includes a reference source for generating a reference voltage and/or a reference current. The reference circuit further includes an activity detector configured to measure an activity level of at least a portion of another circuit coupled to the reference circuit and to generate a control signal representative of the activity level. A controller coupled to the reference source is configured to dynamically change an output impedance of the reference circuit in response to the control signal. The techniques of the present invention thus provide a reference circuit that is capable of dynamically changing an output impedance associated therewith, such that when activity on one or more nodes in the other circuit is detected within a time period, the output impedance of the reference circuit is at a first value which is sufficiently low so as to reduce the likelihood of noise being coupled onto the output of the reference circuit. Alternatively, when essentially no activity on the one or more nodes is detected within the time period, the output impedance of the reference circuit is at a second value which is greater than the first value, thereby reducing power consumption in the reference circuit.

US Patent:

6774698, Aug 10, 2004

Filed:

Jan 30, 2003

Appl. No.:

10/354883

Inventors:

Dipankar Bhattacharya - Macungie PA
Makeshwar Kothandaraman - Emmaus PA
John Christopher Kriz - Palmerton PA
Bernard Lee Morris - Emmaus PA
Stefan Allen Siegel - Fogelsville PA

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H03L 500

US Classification:

327333, 327112, 326 68, 326 81

Abstract:

An apparatus is disclosed for translating a lower voltage signal, utilized in a low voltage integrated circuit, to a higher voltage signal suitable for use in a high voltage circuit. The apparatus includes a low voltage transistor assembly capable of operating in response to the lower voltage signal; a voltage regulator which is configured to limit an applied voltage across the low voltage transistor assembly; and a high voltage converter which is responsive to the operation of the low voltage transistor assembly to generate the higher voltage signal. The voltage regulator includes a reference voltage generator and a voltage limiter.

US Patent:

6850091, Feb 1, 2005

Filed:

Apr 9, 2003

Appl. No.:

10/410009

Inventors:

Bernard Lee Morris - Emmaus PA, US

Assignee:

Agere Systems, Inc. - Allentown PA

International Classification:

H03K 190185

US Classification:

326 86, 326 30, 326 56, 326 90, 326 58, 327108

Abstract:

The present invention provides a bi-directional impedance matching integrated circuit which is couplable through an interface to a channel for signal transmission and reception. The invention includes a first switchable impedance and a second switchable impedance having a respective output impedance and input impedance substantially equal to a channel impedance. An impedance controller is capable of coupling the first switchable impedance to the interface in response to a transmit control signal, coupling the second switchable impedance to the interface in response to a receive control signal, and further capable of uncoupling the first switchable impedance and the second switchable impedance from a power supply and from a ground potential in response to a low power control signal. A mode selector is utilized to provide the transmit control signal, the receive control signal, and the low power control signal.

US Patent:

6977524, Dec 20, 2005

Filed:

Jan 20, 2004

Appl. No.:

10/759253

Inventors:

Carol Ann Huber - Macungie PA, US
Bernard Lee Morris - Emmaus PA, US
Makeshwar Kothandaraman - Kamaraka, IN
Yehuda Smooha - Allentown PA, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H03K019/0175

US Classification:

326 80, 326 81, 326 83, 327534, 361111, 361 56

Abstract:

Using at best a 2. 5V nominal power supply, 3. 3V technology can be used to implement a 5V tolerant open drain output buffer. High voltage and/or current tolerance is achieved with only the 2. 5V power supply. A p-channel FET transistor is connected between a power supply and a node, which in turn is connected to a node between two series output FET transistors. The first transistor is connected between the PAD and node, and the second transistor is connected between the node and ground. The gate of the second transistor is driven from another node formed between a series string of a p-channel FET transistor and an n-channel FET transistor. The other side of the first transistor is connected to the power supply, and the other side of the second transistor is connected to ground. The gates of the transistors of the inverter are tied together and driven by an applied signal.

US Patent:

7002372, Feb 21, 2006

Filed:

Jan 20, 2004

Appl. No.:

10/759162

Inventors:

Carol Ann Huber - Macungie PA, US
Bernard Lee Morris - Emmaus PA, US
Makeshwar Kothandaraman - Karnataka, IN
Yehuda Smooha - Allentown PA, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H03K 19/0175

US Classification:

326 81, 326 80, 326 86

Abstract:

A low voltage, 5V tolerant open drain output buffer having moderate current tolerance capabilities is formed with 3. 3V technology using a nominal power supply of 2. 5V or less. The buffer includes an inverter, a series connection of the current paths of three n-channel FET transistors, and a backgate bias generator. One terminal of the series connection of three transistors is connected to a PAD, and the other terminal of the lower transistor of the series is connected to ground. The bias generator is formed using two p-channel field effect transistors (FETs) that are cross-connected between VDD and the PAD. A gate of a central one of the three transistors is connected to the power supply. An output of the bias generator is connected to a gate of the upper transistor. The inventive buffer may be manufactured using standard 3.