Bin Li Li

US Patent:

6392474, May 21, 2002

Filed:

Aug 30, 2000

Appl. No.:

09/651156

Inventors:

Bin Li - Fairfax VA
Dave C. Lawson - Hartwood VA
Joseph Yoder - Oakton VA

Assignee:

BAE Systems Information and Electronic Systems Integration Inc. - Rockville MD

International Classification:

H03K 500

US Classification:

327551, 327208, 327210

Abstract:

A circuit for filtering single event effect (SEE) induced glitches is disclosed. The circuit for filtering SEE induced glitches comprises an SEE immune latch circuit and a delay element. The SEE immune latch circuit includes a first input, a second input, and an output. The SEE immune latch changes from one state to another state only upon having incoming input signals of identical polarity being applied contemporaneously at both the first input and the second input. The first input of the SEE immune latch circuit is directly connected to a signal input, and the second input of the SEE immune latch circuit is connected to the signal input via the delay element. The delay element provides a signal delay time equal to or greater than a pulse width of an SEE induced glitch but less than a pre-determined pulse width of an incoming signal at the signal input under normal operation. By connecting the delay element between the signal input and the second input of the SEE immune latch circuit, a temporal separation greater that the duration of an SEE induced glitch can be achieved on the data being drive into the first and the second inputs of the SEE immune latch circuit. As a result, SEE induced glitches will not be written into the SEE immune latch circuit.

US Patent:

6944041, Sep 13, 2005

Filed:

Mar 26, 2004

Appl. No.:

10/811454

Inventors:

Bin Li - Chantilly VA, US
Kenneth R. Knowles - Manassas VA, US
David C. Lawson - Haymarket VA, US

Assignee:

BAE Systems Information and Electronic Systems Integration, Inc. - Nashua NH

International Classification:

G11C013/00
G11C011/00

US Classification:

365113, 365163

Abstract:

A circuit for accessing a chalcogenide memory array is disclosed. The chalcogenide memory array includes multiple subarrays with rows and columns formed by chalcogenide storage elements. The chalcogenide memory array is accessed by discrete read and write circuits. Associated with a respective one of the subarrays, each of the write circuits includes an independent write 0 circuit and an independent write 1 circuit. Also associated with a respective one of the subarrays, each of the read circuits includes a sense amplifier circuit. In addition, a voltage level control module is coupled to the read and write circuits to ensure that voltages across the chalcogenide storage elements within the chalcogenide memory array do not exceed a predetermined value during read and write operations.

US Patent:

6965521, Nov 15, 2005

Filed:

Jul 31, 2003

Appl. No.:

10/631174

Inventors:

Bin Li - Chantilly VA, US
Kenneth R. Knowles - Manassas VA, US
David C. Lawson - Haymarket VA, US

Assignee:

BAE Systems, Information and Electronics Systems Integration, Inc. - Nashua NH

International Classification:

G11C011/00

US Classification:

365148, 365163, 365113, 36518901

Abstract:

A read/write circuit for accessing chalcogenide non-volatile memory cells is disclosed. The read/write circuit includes a chalcogenide storage element, a voltage limiting circuit, a current-to-voltage converter, and a buffer circuit. The voltage limiting circuit, which is coupled to the chalcogenide storage element, ensures that voltages across the chalcogenide storage element will not exceed a predetermined value during a read operation. During a read operation, the current-to-voltage converter, which is coupled to the voltage limiting circuit, converts a current pulse read from the chalcogenide storage element to a voltage pulse. By sensing the voltage pulse from the current-to-voltage converter, the buffer circuit can determine a storage state of the chalcogenide storage element.

US Patent:

7099187, Aug 29, 2006

Filed:

Sep 14, 2005

Appl. No.:

11/225953

Inventors:

Bin Li - Chantilly VA, US
Kenneth R. Knowles - Manassas VA, US
David C. Lawson - Haymarket VA, US

Assignee:

BAE Systems Information and Electronic Systems Integration Inc. - Nashua NH
Ovonyx, Inc. - Rochester Hills MI

International Classification:

G11C 11/00

US Classification:

365163, 365113

Abstract:

A read/write circuit for accessing chalcogenide non-volatile memory cells is disclosed. The read/write circuit includes a chalcogenide storage element, a voltage limiting circuit, a current-to-voltage converter, and a buffer circuit. The voltage limiting circuit, which is coupled to the chalcogenide storage element, ensures that voltages across the chalcogenide storage element will not exceed a predetermined value during a read operation. During a read operation, the current-to-voltage converter, which is coupled to the voltage limiting circuit, converts a current pulse read from the chalcogenide storage element to a voltage pulse. By sensing the voltage pulse from the current-to-voltage converter, the buffer circuit can determine a storage state of the chalcogenide storage element.

US Patent:

7916527, Mar 29, 2011

Filed:

Nov 26, 2008

Appl. No.:

12/525482

Inventors:

Bin Li - Chantilly VA, US
Adam Matthew Bumgarner - Duluth GA, US
Daniel Pirkl - Centreville VA, US

Assignee:

BAE Systems Information and Electronic Systems Integration Inc. - Nashua NH
Ovonyx, Inc. - Rochester Hills MI

International Classification:

G11C 11/00

US Classification:

365163, 365203, 36518909

Abstract:

A read reference circuit for a sense amplifier within a chalcogenide memory device is disclosed. The read reference circuit provides a reference voltage level to the sense amplifier for distinguishing between a logical “0” state and a logical “1” state within a chalcogenide memory cell. In conjunction with a precharge circuit, the read reference circuit generates a selectable read reference current to the sense amplifier in order to detect the logical state of the chalcogenide memory cell. The precharge circuit precharges the bitlines of the chalcogenide memory cell before the sense amplifier detects the logical state of the chalcogenide memory cell.

US Patent:

7965098, Jun 21, 2011

Filed:

Dec 10, 2008

Appl. No.:

12/595865

Inventors:

Neil Wood - Centreville CA, US
David Rea - Manassas VA, US
Bin Li - Chantilly VA, US

Assignee:

BAE Systems Information and Electronic Systems Integration Inc. - Nashua NH

International Classification:

H03K 19/003
H03K 19/096
H03L 7/00

US Classification:

326 11, 326 95, 327144

Abstract:

A current mode logic voter circuit includes three two-input split NOR gates. Each two-input split NOR gate receives a corresponding pair of input signals and generates a pair of first output signals responsive to the input signals. A three input split NOR gate is coupled to the two-input split NOR gates to receive the first output signals and generates a second pair of output signals responsive to the first output signals from the two-input split NOR gates. The two and three-input split NOR gates can be formed from current mode logic buffer circuits, and in one embodiment in the three-input split NOR gate the buffer circuits are hardened.

US Patent:

7965541, Jun 21, 2011

Filed:

Nov 25, 2008

Appl. No.:

12/525458

Inventors:

Bin Li - Chantilly VA, US
John C. Rodgers - Fairfax VA, US
Nadim F. Haddad - Oakton VA, US

Assignee:

BAE Systems Information and Electronic Systems Integration Inc. - Nashua NH
Ovonyx, Inc. - Rochester Hills MI

International Classification:

G11C 11/00

US Classification:

365156, 365154, 365163

Abstract:

A non-volatile single-event upset (SEU) tolerant latch is disclosed. The non-volatile SEU tolerant latch includes a first and second inverters connected to each other in a cross-coupled manner. The gates of transistors within the first inverter are connected to the drains of transistors within the second inverter via a first feedback resistor. Similarly, the gates of transistors within the second inverter are connected to the drains of transistors within the first inverter via a second feedback resistor. The non-volatile SEU tolerant latch also includes a pair of chalcogenide memory elements connected to the inverters for storing information.

US Patent:

7986550, Jul 26, 2011

Filed:

Nov 26, 2008

Appl. No.:

12/525510

Inventors:

Bin Li - Chantilly VA, US
Adam Matthew Bumgarner - Duluth GA, US

Assignee:

BAE Systems Information and Electronics Systems Integration Inc. - Nashua NH
Ovonyx, Inc. - Rochester Hills MI

International Classification:

G11C 7/00

US Classification:

365163, 36518915, 365151

Abstract:

An analog access circuit for characterizing chalcogenide memory cells is disclosed. The analog access circuit includes an analog access control module, an address and data control module, and an analog cell access and current monitoring module. The analog access control module selectively controls whether a normal memory access or an analog memory access should be performed on a specific chalcogenide memory cell. The address and data control module allows a normal memory access to the chalcogenide memory cell according to an input address. The analog cell access and current monitoring module performs an analog memory access to the chalcogenide memory cell according to the input address, and monitors a reference current from a sense amplifier associated with the chalcogenide memory cell.