Binh Thanh Hoang

US Patent:

7434182, Oct 7, 2008

Filed:

Jul 14, 2005

Appl. No.:

11/181442

Inventors:

Kenneth O. Brinson - Austin TX, US
Sanjay Gupta - Austin TX, US
Binh T. Hoang - Austin TX, US
James M. Stafford - Liberty Hill TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50
G06F 9/45
H03K 17/693

US Classification:

716 4, 716 5, 716 16

Abstract:

A method is provided in which a previously verified SoC is coupled to a SoC under test via a communication bus or other type of communication interface. The previously verified SoC is provided with the same test stimuli as the SoC under test and thus, generates expected test results data. The test stimuli are sent to the SoC under test via a peripheral communication interface between the previously verified SoC and the SoC under test. The SoC under test generates actual test result data that is output to the previously verified SoC. The previously verified SoC may then compare the expected test results data with the actual test result data generated by the SoC under test to determine if they match. If the two sets of data do not match, then a mismatch notification may be generated and output.

US Patent:

8024699, Sep 20, 2011

Filed:

Aug 21, 2008

Appl. No.:

12/195716

Inventors:

Kenneth O. Brinson - Austin TX, US
Sanjay Gupta - Austin TX, US
Binh T. Hoang - Austin TX, US
James M. Stafford - Liberty Hill TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/455
G06F 17/50

US Classification:

716138, 716111

Abstract:

Mechanisms are provided in which a previously verified SoC is coupled to a SoC under test via a communication bus or other type of communication interface. The previously verified SoC is provided with the same test stimuli as the SoC under test and thus, generates expected test results data. The test stimuli are sent to the SoC under test via a peripheral communication interface between the previously verified SoC and the SoC under test. The SoC under test generates actual test results data that is output to the previously verified SoC. The previously verified SoC may then compare the expected test results data with the actual test result data generated by the SoC under test to determine if they match. If the two sets of data do not match, then a mismatch notification may be generated and output.

US Patent:

57371717, Apr 7, 1998

Filed:

Jul 15, 1996

Appl. No.:

8/680451

Inventors:

Marvin Lawrence Buller - Austin TX
Gary Dale Carpenter - Pflugerville TX
Binh Thai Hoang - Round Rock TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H02H 504

US Classification:

361103

Abstract:

Systems and methods for reducing the thermal stresses between an integrated circuit package and a printed circuit board, each having different thermal coefficients of expansion, to minimize thermal fatigue induced by power management cycling. The thermal impedance of the convection cooling system used with the integrated circuit package is switched with the state of the power management signal. A fan on the integrated circuit package heat sink is energized when the integrated circuit is operated in a high power mode and disabled when the integrated circuit is in a low power mode initiated by the power management system. The switching is directly responsive to the power management system and without regard to integrated circuit package temperature. The switching of the fan alters the thermal impedance to reduce the extremes of the temperature excursion and to materially reduce the rate of change of temperature experienced by the integrated circuit package. Relative temperature induced stresses on the connection between the printed circuit board and integrated circuit package are decreased.

US Patent:

60264691, Feb 15, 2000

Filed:

Sep 19, 1997

Appl. No.:

8/933700

Inventors:

Binh Thai Hoang - Round Rock TX
Cuong Thanh Nguyen - Austin TX
Howard Carl Tanner - Austin TX
Gary Yuh Tsao - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1200

US Classification:

711118

Abstract:

A module type distinguishing apparatus and method for differentiating between modules based upon the presence or absence of a pulling resistor at a specified pin connection of the modules. A high impedance pulling resistance is connected to the line and is subject to sensing while a tri-state mode of operation is initiated in the module. The presence or absence of the pulling resistor in the module is detected and recorded in a register. Differentiation between module types is accomplished based upon the binary state of the data in the register. In a particularized implementation, industry standard L2 cache modules are distinguished as to tag bit size depending on the presence or absence of a pulling resistor as detected during tri-state operation of a tag output pin.

US Patent:

58154558, Sep 29, 1998

Filed:

Sep 19, 1997

Appl. No.:

8/933701

Inventors:

Keith Andre Braithwaite - Pflugerville TX
Gary Dale Carpenter - Pflugerville TX
Binh Thai Hoang - Round Rock TX
Cuong Thanh Nguyen - Austin TX
Howard Carl Tanner - Austin TX
Gary Yuh Tsao - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 1300

US Classification:

365229

Abstract:

A power supply interface suitable to provide voltages of appropriate magnitude to a static random access memory (SRAM) device from a combination of independent sources including a main power supply, an auxiliary power supply, and a battery. The voltages from the interface are at levels consistent with the SRAM modes of operation. During limited voltage tolerance read and write access operations, main power supply voltage is provided through a low forward voltage drop switched metal oxide field effect transistor (MOSFET). Parasitic paths, potentially producible by the transistor and affecting the battery source of power, are eliminated through the use of a second, complementary MOSFET. The second MOSFET is directly responsive to a POWERGOOD signal from the main power supply, indicating both an "on" state and an appropriate voltage level of the main power supply.