Binh E Ly

US Patent:

57233551, Mar 3, 1998

Filed:

Jan 17, 1997

Appl. No.:

8/785234

Inventors:

Binh Ly - San Jose CA

Assignee:

Programmable Microelectronics Corp.

International Classification:

H01L 218247

US Classification:

437 56

Abstract:

A semiconductor fabrication process allows for the fabrication of high-voltage transistors, logic transistors, and memory cells where, as required for sub-0. 3 micron device geometries, the gate oxide of the logic transistors is thinner than the tunnel oxide thickness of the non-volatile memory cells without the undesirable contamination of the gate oxide of the logic transistors or contamination of the tunnel oxide of the memory cells. In one embodiment, the tunnel oxide of the memory cells is grown to a desired thickness. In a next step, a layer of doped polysilicon which will serve as the floating gate of the memory cell(s) is immediately deposited over the tunnel oxide of the memory cells, thereby protecting the tunnel oxide from contamination in subsequent masking and etching steps. The gate oxide of the logic transistors and the gate oxide of the high-voltage transistors are then grown to a desired thickness.

US Patent:

20190189231, Jun 20, 2019

Filed:

Feb 25, 2019

Appl. No.:

16/285037

Inventors:

- Portland OR, US
Nguyen Duc Bui - San Jose CA, US
Binh Ly - San Jose CA, US

International Classification:

G11C 17/16
H01L 27/11582
G11C 17/18
H01L 49/02
H01L 27/112

Abstract:

A non-volatile programmable bitcell has a read enable device with a source coupled with a bitline, an anti-fuse device with a gate coupled with a first write line, a drain coupled with a supply voltage and a source coupled with a drain of the read enable device. The bitcell has a fuse device coupled between a second write line and the drain of the read enable device. A magnitude of current flowing in the bitline, when the read enable device is enabled for reading, is dependent both on (1) a voltage level applied to the first write line and anti-fuse device state and on (2) a voltage level applied to the second write line and fuse device state. Usages include in a memory array, such as for FPGA configuration memory. The bitcell can be used as a multi-time programmable element, or to store multiple bit values.

US Patent:

20180019018, Jan 18, 2018

Filed:

Sep 26, 2017

Appl. No.:

15/715807

Inventors:

- Portland OR, US
Nguyen Duc Bui - San Jose CA, US
Binh Ly - San Jose CA, US

International Classification:

G11C 17/16
H01L 27/112
G11C 17/18

Abstract:

A non-volatile programmable bitcell has a read enable device with a source coupled with a bitline, an anti-fuse device with a gate coupled with a first write line, a drain coupled with a supply voltage and a source coupled with a drain of the read enable device. The bitcell has a fuse device coupled between a second write line and the drain of the read enable device. A magnitude of current flowing in the bitline, when the read enable device is enabled for reading, is dependent both on (1) a voltage level applied to the first write line and anti-fuse device state and on (2) a voltage level applied to the second write line and fuse device state. Usages include in a memory array, such as for FPGA configuration memory. The bitcell can be used as a multi-time programmable element, or to store multiple bit values.