Binh D Pham

US Patent:

20220261351, Aug 18, 2022

Filed:

May 6, 2022

Appl. No.:

17/738919

Inventors:

- Santa Clara CA, US
Venkata Krishnan - Ashland MA, US
Andrew J. Herdrich - Hillsboro OR, US
Ren Wang - Portland OR, US
Robert G. Blankenship - Tacoma WA, US
Vedaraman Geetha - Fremont CA, US
Shrikant M. Shah - Chandler AZ, US
Marshall A. Millier - Banks OR, US
Raanan Sade - Haifa, IL
Binh Q. Pham - Hillsboro OR, US
Olivier Serres - Hudson MA, US
Christopher B. Wilkerson - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/0868
G06F 12/0897
G06F 3/06
G06F 12/0811
G06F 12/0871

Abstract:

Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.

US Patent:

20210049102, Feb 18, 2021

Filed:

Mar 30, 2020

Appl. No.:

16/834845

Inventors:

- Santa Clara CA, US
Venkata Krishnan - Ashland MA, US
Andrew J. Herdrich - Hillsboro OR, US
Ren Wang - Portland OR, US
Robert G. Blankenship - Tacoma WA, US
Vedaraman Geetha - Fremont CA, US
Shrikant M. Shah - Chandler AZ, US
Marshall A. Millier - Banks OR, US
Raanan Sade - Haifa, IL
Binh Q. Pham - Hillsboro OR, US
Olivier Serres - Hudson MA, US
Christopher B. Wilkerson - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/0868
G06F 12/0897
G06F 3/06
G06F 12/0811
G06F 12/0871

Abstract:

Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.

US Patent:

20200104259, Apr 2, 2020

Filed:

Sep 28, 2018

Appl. No.:

16/147346

Inventors:

- Santa Clara CA, US
Lawrence C. Stewart - Wayland MA, US
Binh Pham - Hillsboro OR, US
Andrew Herdrich - Hillsboro OR, US
Venkata Krishnan - Ashland MA, US
Anil Vasudevan - Portland OR, US
Joseph Nuzman - Haifa, IL
Tsung-Yuan Tai - Portland OR, US

International Classification:

G06F 12/0862
G06F 12/0817
G06F 12/0842

Abstract:

A snapshot prefetcher to perform snapshot prefetching to improve performance of snapshot read operations. An apparatus embodiment includes a snapshot read tracking circuitry to track snapshot read requests made by a first processor core to read a plurality of cache lines, and to detect a snapshot read access stream based on the tracked snapshot read requests. A snapshot prefetch issuing circuitry of the apparatus to issue, based on the detected snapshot read access stream, one or more snapshot prefetch requests, including a first snapshot prefetch request to prefetch data from a first cache line stored in, and owned exclusively by, a first storage location outside the first processor core. The snapshot prefetch issuing circuitry further to store the prefetched data in a second storage location within the first processor core, wherein after the prefetch, exclusive ownership of the first cache line is to remain with the first storage location.

US Patent:

20200081718, Mar 12, 2020

Filed:

Nov 12, 2019

Appl. No.:

16/680907

Inventors:

- Santa Clara CA, US
Binh Pham - Hillsboro OR, US
Patrick Lu - Chandler AZ, US

International Classification:

G06F 9/38
G06F 9/30

Abstract:

In an embodiment, a processor includes a branch prediction circuit and a plurality of processing engines. The branch prediction circuit is to: detect a coherence operation associated with a first memory address; identify a first branch instruction associated with the first memory address; and predict a direction for the identified branch instruction based on the detected coherence operation. Other embodiments are described and claimed.

US Patent:

20190303162, Oct 3, 2019

Filed:

Mar 29, 2018

Appl. No.:

15/940408

Inventors:

Christopher Wilkerson - Portland OR, US
Binh Pham - Hillsboro OR, US
Patrick Lu - Chandler AZ, US

International Classification:

G06F 9/38
G06F 9/30

Abstract:

In an embodiment, a processor includes a branch prediction circuit and a plurality of processing engines. The branch prediction circuit is to: detect a coherence operation associated with a first memory address; identify a first branch instruction associated with the first memory address; and predict a direction for the identified branch instruction based on the detected coherence operation. Other embodiments are described and claimed.

US Patent:

20190004958, Jan 3, 2019

Filed:

Jun 30, 2017

Appl. No.:

15/640060

Inventors:

- Santa Clara CA, US
Venkata Krishnan - Ashland MA, US
Andrew J. Herdrich - Hillsboro OR, US
Ren Wang - Portland OR, US
Robert G. Blankenship - Tacoma WA, US
Vedaraman Geetha - Fremont CA, US
Shrikant M. Shah - Chandler AZ, US
Marshall A. Millier - Banks OR, US
Raanan Sade - Haifa, IL
Binh Q. Pham - Hillsboro OR, US
Olivier Serres - Hudson MA, US
Christopher B. Wilkerson - Portland OR, US

International Classification:

G06F 12/0868
G06F 12/0811
G06F 3/06
G06F 12/0871

Abstract:

Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.