Bradford W Robbins

US Patent:

7017087, Mar 21, 2006

Filed:

Dec 29, 2000

Appl. No.:

09/751633

Inventors:

Michael C. Panis - Brookline MA, US
Bradford B. Robbins - Wellesley MA, US

Assignee:

Teradyne, Inc. - Boston MA

International Classification:

G01R 31/28

US Classification:

714716

Abstract:

A system and method for economically yet thoroughly testing serial ports of electronic devices includes a receiver and a transmitter. The receiver is coupled to a TX line of a device under test for receiving an input serial bit stream from the device under test. The transmitter is coupled to a RX line of the device under test for providing an output serial bit stream to the device under test. The receiver is coupled to the transmitter for establishing a loopback connection. A time distortion circuit is interposed between the receiver and the transmitter, for adding predetermined amounts of timing distortion to the output serial bit stream. In addition, a selector is interposed between the receiver and the transmitter, for selecting between the receiver and a direct input. The direct input provides an algorithmic test signal that differs from the input serial bit stream received by the receiver. The direct input thus allows a tester to exercise the device under test with a test signal that differs from the signal that the device under test generates.

US Patent:

7337377, Feb 26, 2008

Filed:

Dec 22, 2005

Appl. No.:

11/315974

Inventors:

Michael C. Panis - Brookline MA, US
Bradford B. Robbins - Wellesley MA, US

Assignee:

Teradyne, Inc. - North Reading MA

International Classification:

G01R 31/28

US Classification:

714716

Abstract:

A system and method for economically yet thoroughly testing serial ports of electronic devices includes a receiver and a transmitter. The receiver is coupled to a TX line of a device under test for receiving an input serial bit stream from the device under test. The transmitter is coupled to a RX line of the device under test for providing an output serial bit stream to the device under test. The receiver is coupled to the transmitter for establishing a loopback connection. A time distortion circuit is interposed between the receiver and the transmitter, for adding predetermined amounts of timing distortion to the output serial bit stream. In addition, a selector is interposed between the receiver and the transmitter, for selecting between the receiver and a direct input. The direct input provides an algorithmic test signal that differs from the input serial bit stream received by the receiver. The direct input thus allows a tester to exercise the device under test with a test signal that differs from the signal that the device under test generates.

US Patent:

55661882, Oct 15, 1996

Filed:

Mar 29, 1995

Appl. No.:

8/413063

Inventors:

Bradford B. Robbins - Wellesley MA
Benjamin J. Brown - Westlake Village CA
Peter A. Reichert - Thousand Oaks CA

Assignee:

Teradyne, Inc. - Boston MA

International Classification:

G01R 3128

US Classification:

371 27

Abstract:

Automatic test equipment with a programmable timing generator. In the timing generator, the required delay is split into a course delay, a frequency adjustment delay, and a fine delay. The fine delays for successive cycles are temporarily stored. As the course delays pass, the fine delays are retrieved and used to generate edge signals. The frequency adjustment delay is used to offset the time at which the fine delay is retrieved by a fraction of a the resolution of the course delay. This arrangement allows the fine delay values to be retrieved at a higher rate than the rate at which the signals representing the required delays were generated. With this arrangement, the edges can be generated in a high frequency burst mode even though much of the timing generator is implemented with circuitry that has a lower operating frequency. A significant cost savings results by providing high frequency operation with less expensive components of lower operating frequency.