Bradley Waters

US Patent:

6493837, Dec 10, 2002

Filed:

Jul 16, 1999

Appl. No.:

09/354840

Inventors:

Jee Fung Pang - Woodinville WA
Bradley Michael Waters - Woodinville WA

Assignee:

Microsoft Corporation - Redmond WA

International Classification:

G06F 1134

US Classification:

714 45, 714 18, 714 20, 707202, 707204

Abstract:

An event tracing program generally receives performance data about an event occurring on the computer system from a data producer program. The event tracing program responds by recording the event performance data in one of a set of a log buffers. When a log buffer becomes full, the event tracing program places the log buffer on a buffer flush list. The filled buffer is then written out to a more permanent storage medium, such as a disk. From time to time, the event tracing program may also transfer a buffer to the flush list prior to becoming full after a time-out period. To prevent a buffer from being flushed while event performance data is being recorded in the buffer, a reference count is incremented prior to the record operation to signify that the buffer is currently being modified. For high performance on multiprocessor systems, the buffers are allocated per processor to minimize data sharing among processors.

US Patent:

RE40989, Nov 17, 2009

Filed:

Nov 12, 2004

Appl. No.:

10/988447

Inventors:

Neel K. Jain - Redmond WA, US
Bradley M. Waters - Woodinville WA, US
Mahlon David Fields - Kirkland WA, US

Assignee:

Microsoft Corporation - Redmond WA

International Classification:

G06F 12/00

US Classification:

707203, 707 1, 707 2, 707 3, 707 8, 707201

Abstract:

Performing atomic operations on data entities having an arbitrary size is disclosed. Version data is associated with a data entity. The version data is saved to a first attribute. The data entity is then accessed. The saved version data is compared to the current version data. If the two are equal, the data entity is valid.

US Patent:

7747820, Jun 29, 2010

Filed:

Jun 15, 2007

Appl. No.:

11/818727

Inventors:

Bradford Beckmann - Redmond WA, US
Bradley M. Waters - Woodinville WA, US

Assignee:

Microsoft Corporation - Redmond WA

International Classification:

G06F 13/00
G06F 13/28

US Classification:

711118

Abstract:

A processor cache is indexed by a group of distinct page colors. The use of this cache by different working sets is controlled using page coloring. Translations of virtual addresses of the instructions and/or data of a working set are constrained to physical addresses the page colors of which are in a subgroup of the group of distinct page colors.

US Patent:

7913040, Mar 22, 2011

Filed:

May 17, 2010

Appl. No.:

12/781172

Inventors:

Bradford Beckmann - Redmond WA, US
Bradley M. Waters - Woodinville WA, US

Assignee:

Microsoft Corporation - Redmond WA

International Classification:

G06F 13/00

US Classification:

711118, 711E12058

Abstract:

A processor cache is indexed by a group of distinct page colors. The use of this cache by different working sets is controlled using page coloring. Translations of virtual addresses of the instructions and/or data of a working set are constrained to physical addresses the page colors of which are in a subgroup of the group of distinct page colors.

US Patent:

7975107, Jul 5, 2011

Filed:

Jun 22, 2007

Appl. No.:

11/821140

Inventors:

Bradford Beckmann - Redmond WA, US
Bradley M. Waters - Woodinville WA, US

Assignee:

Microsoft Corporation - Redmond WA

International Classification:

G06F 13/00
G06F 12/02

US Classification:

711118, 711122, 711137, 711E12004

Abstract:

Software assists a processor subsystem in making cache replacement decisions by providing an intermediary with information regarding how instructions and/or data of a working set are expected to be used and accessed by the software. The intermediary uses this information along with its knowledge of system requirements, policy and the cache configuration to determine cache usage and management hints for the working sets. The cache usage and management hints are passed by the intermediary to the processor subsystem.

US Patent:

8006055, Aug 23, 2011

Filed:

Mar 4, 2008

Appl. No.:

12/042261

Inventors:

Bradley M Waters - Woodinville WA, US
Niklas Gustafsson - Bellevue WA, US

Assignee:

Microsoft Corporation - Redmond WA

International Classification:

G06F 12/00

US Classification:

711163, 711156

Abstract:

Protection entries and techniques for providing fine granularity computer memory protection are described herein. A method of protecting a computer memory may include separating or parsing the computer memory, containing data or code, into blocks and creating protection entries for each block. The protection entries optionally include a reference field for identifying a block of memory, and a protection field for specifying one or more levels of access to the identified block of memory. The protection entries may then be used to pass messages between various system entities, the messages specifying one or more levels of access to the one or more blocks of memory or code.

US Patent:

20070101338, May 3, 2007

Filed:

Oct 31, 2005

Appl. No.:

11/263318

Inventors:

Abdelsalam Heddaya - Bellevue WA, US
Stephan Doll - Seattle WA, US
Bradley Waters - Woodinville WA, US
William Barnes - Redmond WA, US

Assignee:

MICROSOFT CORPORATION - Redmond WA

International Classification:

G06F 9/46

US Classification:

718104000

Abstract:

A computer configured for managing multiple processing threads is susceptible to deadlocks or hangs when resources needed by one process are locked by another process that is not progressing. Locking relationships are created and released so quickly that rigidly monitoring these relationships would consume more computer power than are being monitored. An approach to determining the existence of a deadlock or hang uses a first ‘snapshot’ showing an approximation of locking relationships and then verifies a deadlock or hang using a second snapshot to determine if a suspected deadlock or hang is still present.

US Patent:

20130290667, Oct 31, 2013

Filed:

Apr 27, 2012

Appl. No.:

13/458355

Inventors:

Amol Dilip Dixit - Bellevue WA, US
Bradley Michael Waters - Woodinville WA, US

Assignee:

MICROSOFT CORPORATION - Redmond WA

International Classification:

G06F 12/02

US Classification:

711173, 711E12002

Abstract:

Systems and techniques of the management of the allocation of a plurality of memory elements stored within a plurality of lockless list structures are presented. These lockless list structures (such as Slists) may be made accessible within an operating system environment of a multicore processor—and may be partitioned within the system. Memory elements may also be partitioned among these lockless list structures. When a core processor (or other processing element) makes a request for allocating a memory element to itself, the system and/or method may search among the lockless list structures for an available memory element. When a suitable and/or available memory element is found, the system may allocate the available memory element to requesting core processor. Dynamically balancing of memory elements may occur according to a suitable balancing metric, such as maintain substantial numerical equality of memory elements or avoid over-allocation of resources.