Brent D Leback

US Patent:

20050114560, May 26, 2005

Filed:

Oct 21, 2004

Appl. No.:

10/972083

Inventors:

Ron Coleman - Beaverton OR, US
Brent LeBack - Portland OR, US
Stuart Hawkinson - Portland OR, US
Richard Rubinstein - Santa Cruz CA, US

Assignee:

Marger Johnson & McCollom, P.C. - Portland OR

International Classification:

G06F013/28

US Classification:

710022000

Abstract:

An architecture is shown where an execution unit is tightly coupled to a shared, reconfigurable memory system. Sequence control signals drive a DMA controller and address generator to control the transfer of data from the shared memory to a bus interface unit (BIU). The sequence control signals also drive a data controller and address generator which controls transfer of data from the shared memory to an execution unit interface (EUI). The EUI is connected to the execution unit operates under control of the data controller and address generator to transfer vector data to and from the shared memory. The shared memory is configured to swap memory space in between the BIU and the execution unit so as to support continuous execution and I/O. A local fast memory is coupled to the execution unit. A local address generator controls the transfer of scalar data between the local fast memory and the execution unit. The execution unit, local fast memory and local address generator form a fast memory path that is not dependent upon the slower data path between the execution unit and shared memory. The fast memory path provides for fast execution of scalar operations in the execution unit and rapid state storage and retrieval for operations in the execution unit.

US Patent:

6895452, May 17, 2005

Filed:

Oct 16, 1998

Appl. No.:

09/174057

Inventors:

Ron Coleman - Beaverton OR, US
Brent LeBack - Portland OR, US
Stuart Hawkinson - Portland OR, US
Richard Rubinstein - Santa Cruz CA, US

Assignee:

Marger Johnson & McCollom, P.C. - Portland OR

International Classification:

G06F015/76

US Classification:

710 22, 710 65, 712 10, 712220

Abstract:

An architecture is shown where an execution unit is tightly coupled to a shared, reconfigurable memory system. Sequence control signals drive a DMA controller and address generator to control the transfer of data from the shared memory to a bus interface unit (BIU). The sequence control signals also drive a data controller and address generator which controls transfer of data from the shared memory to an execution unit interface (EUI). The EUI is connected to the execution unit operates under control of the data controller and address generator to transfer vector data to and from the shared memory. The shared memory is configured to swap memory space in between the BIU and the execution unit so as to support continuous execution and I/O. A local fast memory is coupled to the execution unit. A local address generator controls the transfer of scalar data between the local fast memory and the execution unit.