Bret Leslie Toll from 2868 Lorie Dr, Beaverton, OR 97124, age 58, Phone: 5036812116

Resumes

Distinguished Engineer - Cpu Architecture

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Location:

2868 northeast Lorie Dr, Hillsboro, OR 97124

Industry:

Computer Hardware

Work:

Ampere
Distinguished Engineer - Cpu Architecture
Intel Corporation Aug 1, 1993 - Oct 2018
Cpu Architect - Senior Principal Engineer
Prometheus Products Aug 1992 - Aug 1993
Design Engineer
Mentor Graphics Feb 1990 - Jul 1992
Production Testing Engineer

Education:

Oregon Graduate Institute 1995 - 2000
Masters, Computer Engineering, Architecture Portland State University 1985 - 1990
Bachelors, Bachelor of Science, Electrical Engineering

Skills:

Processors
Microprocessors
Computer Architecture
Microarchitecture
Debugging
Verilog
Intel
Hardware Architecture
Soc
Vlsi
Logic Design
Rtl Design
Semiconductors
Asic
Linux
Architecture
Testing
Application Specific Integrated Circuits

Us Patents

Method And Apparatus For Disabling A Clock Signal Within A Multithreaded Processor
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US Patent:

6357016, Mar 12, 2002
Filed:

Dec 9, 1999
Appl. No.:

09/458589
Inventors:

Dion Rodgers - Hillsboro OR
Bret Toll - Hillsboro OR
Aimee Wood - Hillsboro OR
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 108
US Classification:

713601
Abstract:

A method includes maintaining an indication of a pending event with respect to each of a number of threads supported within a multithreaded processor. An indication is also maintained of an active or inactive state for each of the multiple threads. A clock disable condition is detected. This clock disable condition may be indicated by the absence of pending events with respect to each of the multiple threads and an inactive state for each of the multiple threads. A clocks signal, if enabled, is then disabled with respect to at least one functional unit within the multithreaded processor responsive to the detection of the clock disable condition.

Method And Apparatus For Power Mode Transition In A Multi-Thread Processor
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US Patent:

6775786, Aug 10, 2004
Filed:

Sep 12, 2001
Appl. No.:

09/951908
Inventors:

Bret L. Toll - Tigard OR
Alan B. Kyker - Portland OR
Stephen H. Gunther - Folsom CA
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 126
US Classification:

713323
Abstract:

A method and apparatus for power mode transition in a multi-thread processor. A first indication is issued, including a first identifier associated with a first logical processor in a processor, that the first logical processor has entered a power mode. A second indication is issued, including a second identifier associated with a second logical processor in the processor, that the second logical processor has entered the power mode. The indications may be, for example, stop grant acknowledge special bus cycles indicating that the logical processors have entered a stop grant mode. The processor may be transitioned to a sleep mode when both the first and second indications have been issued.

Method And Apparatus For Disabling A Clock Signal Within A Multithreaded Processor
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US Patent:

6883107, Apr 19, 2005
Filed:

Mar 8, 2002
Appl. No.:

10/095357
Inventors:

Dion Rodgers - Hillsboro OR, US
Bret Toll - Hillsboro OR, US
Aimee Wood - Hillsboro OR, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F001/08
G06F001/32
US Classification:

713601, 713322
Abstract:

A method includes maintaining an indication of a pending event with respect to each of a number of threads supported within a multithreaded processor. An indication is also maintained of an active or inactive state for each of the multiple threads. A clock disable condition is detected. This clock disable condition may be indicated by the absence of pending events with respect to each of the multiple threads and an inactive state for each of the multiple threads. A clocks signal, if enabled, is then disabled with respect to at least one functional unit within the multithreaded processor responsive to the detection of the clock disable condition.

Method And Apparatus For Power Mode Transition In A Multi-Thread Processor
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US Patent:

6981163, Dec 27, 2005
Filed:

Jul 7, 2004
Appl. No.:

10/887488
Inventors:

Bret L. Toll - Tigard OR, US
Alan B. Kyker - Portland OR, US
Stephen H. Gunther - Folsom CA, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F001/26
US Classification:

713323
Abstract:

A method and apparatus for power mode transition in a multi-thread processor. A first indication is issued, including a first identifier associated with a first logical processor in a processor, that the first logical processor has entered a power mode. A second indication is issued, including a second identifier associated with a second logical processor in the processor, that the second logical processor has entered the power mode. The indications may be, for example, stop grant acknowledge special bus cycles indicating that the logical processors have entered a stop grant mode. The processor may be transitioned to a sleep mode when both the first and second indications have been issued.

Method And Apparatus For Decompressing Relative Addresses
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US Patent:

7010665, Mar 7, 2006
Filed:

Jun 27, 2002
Appl. No.:

10/185513
Inventors:

Bret L. Toll - Tigard OR, US
Michael J. St. Clair - Portland OR, US
John Allan Miller - Portland OR, US
Hitesh Ahuja - Thousand Oaks CA, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 12/02
US Classification:

711220, 711215
Abstract:

A method and apparatus for decompressing relative addresses. A compressed relative address is retrieved from one or more micro-operation entries of a micro-operation storage and an uncompressed relative address is reconstructed from the compressed relative address and an instruction pointer (IP) address associated with the head of the micro-operation storage line in which the compressed relative address was stored. IP-relative addresses may be computed in a manner similar to relative branch targets, then compressed and stored in one or more micro-operation entries of a micro-operation storage line to be reconstructed later according to an IP address associated with the respective micro-operation storage line in which their compressed counterpart was stored.

Method And Apparatus For Representation Of An Address In Canonical Form
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US Patent:

7103751, Sep 5, 2006
Filed:

Jun 27, 2002
Appl. No.:

10/186004
Inventors:

Bret L. Toll - Hillsboro OR, US
John Alan Miller - Portland OR, US
Michael A. Fetterman - Hillsboro OR, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 12/00
US Classification:

711220, 711202, 711203, 712216
Abstract:

A method and apparatus for representing an address in canonical form. The address is received and an error indicator is computed according to whether the address is received in a correct canonical form. The error indicator is stored together with a portion of the address, the portion being less than the entire address. The error indicator, together with the portion of the address stored, represent the address received.

Method And Apparatus For Compressing Relative Addresses
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US Patent:

7111148, Sep 19, 2006
Filed:

Jun 27, 2002
Appl. No.:

10/185895
Inventors:

Bret L. Toll - Tigard OR, US
Michael J. St. Clair - Portland OR, US
John Allan Miller - Portland OR, US
Hitesh Ahuja - Thousand Oaks CA, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 9/26
US Classification:

711220, 712211
Abstract:

A method and apparatus for compressing relative addresses and for storage of compressed relative addresses. A relative virtual address is computed in a particular stage of a processor pipeline and then compressed according to one or more compression techniques for storage in a micro-operation storage. A compressed relative address is retrieved from one or more micro-operation entries of the micro-operation storage and an uncompressed virtual address is reconstructed from the compressed relative address and an instruction pointer (IP) address associated with the head of the micro-operation storage line in which the compressed relative address was stored. IP-relative addresses may be computed in a manner similar to relative branch targets, then compressed and stored in one or more micro-operation entries of a micro-operation storage line to be reconstructed later according to an IP address associated with the respective micro-operation storage line in which their compressed counterpart was stored.

Method And Apparatus For Performing Multiply-Add Operations On Packed Byte Data
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US Patent:

7430578, Sep 30, 2008
Filed:

Jun 30, 2003
Appl. No.:

10/610831
Inventors:

Eric Debes - Santa Clara CA, US
William W. Macy - Palo Alto CA, US
Jonathan J. Tyler - Austin TX, US
James Coke - Shingle Springs CA, US
Frank Binns - Hillsboro OR, US
Scott Rodgers - Hillsboro OR, US
Peter Ruscito - Folsom CA, US
Bret Toll - Hillsboro OR, US
Vesselin Naydenov - Folsom CA, US
Masood Tahir - Orangevale CA, US
David Jackson - Folsom CA, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 7/38
US Classification:

708603
Abstract:

A method and apparatus for including in a processor instructions for performing multiply-add operations on packed byte data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed byte data and a second packed byte data. The processor performs operations on data elements in said first packed byte data and said second packed byte data to generate a third packed data in response to receiving an instruction. A plurality of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed byte data.