Brett M Diamond

US Patent:

7640805, Jan 5, 2010

Filed:

Dec 18, 2006

Appl. No.:

11/640345

Inventors:

Brett M. Diamond - Monroeville PA, US
Matthew A. Zeleznik - Pittsburgh PA, US
Jan E. Vandemeer - Bethel Park PA, US
Kaigham J. Gabriel - Pittsburgh PA, US

Assignee:

Akustica, Inc. - Pittsburgh PA

International Classification:

G01P 15/125

US Classification:

7351432

Abstract:

Provided is a micro-electromechanical-system (MEMS) device including a substrate; at least one semiconductor layer provided on the substrate; a circuit region including at least one chip containing drive/sense circuitry, the circuit region provided on the at least one semiconductor layer; a support structure attached to the substrate; at least one elastic device attached to the support structure; a proof-mass suspended by the at least one elastic device and free to move in at least one of the x-, y-, and z-directions; at least one top electrode provided on the at least one elastic device; and at least one bottom electrode located beneath the at least one elastic device such that an initial capacitance is generated between the at least one top and bottom electrodes, wherein the drive/sense circuitry, proof-mass, supporting structure, and the at least one top and bottom electrodes are fabricated on the at least one semiconductor layer.

US Patent:

7863714, Jan 4, 2011

Filed:

Jun 5, 2006

Appl. No.:

11/446397

Inventors:

Brett M. Diamond - Pittsburgh PA, US
Matthew A. Zeleznik - Pittsburgh PA, US

Assignee:

Akustica, Inc. - Pittsburgh PA

International Classification:

H01L 23/552

US Classification:

257660, 257414, 257499, 438149, 438606

Abstract:

An integrated circuit device includes a semiconductor die, the semiconductor die including a semiconductor substrate, driving/control circuitry disposed along a peripheral region of the semiconductor die, a MEMS device disposed within a central region of the semiconductor die, and a barrier disposed between the driving/control circuitry and the MEMS device.

US Patent:

8094980, Jan 10, 2012

Filed:

Jan 4, 2010

Appl. No.:

12/651551

Inventors:

Brett M. Diamond - Monroeville PA, US
Matthew A. Zeleznik - Pittsburgh PA, US
Jan E. Vandemeer - Bethel Park PA, US
Kaigham J. Gabriel - Pittsburgh PA, US

Assignee:

Akustica, Inc. - Pittsburgh PA

International Classification:

G02B 6/42
G02B 26/08

US Classification:

385 18, 3592231, 310309

Abstract:

Provided is a micro-electromechanical-system (MEMS) device including a substrate; at least one semiconductor layer provided on the substrate; a circuit region including at least one chip containing drive/sense circuitry, the circuit region provided on the at least one semiconductor layer; a support structure attached to the substrate; at least one elastic device attached to the support structure; a proof-mass suspended by the at least one elastic device and free to move in at least one of the x-, y-, and z-directions; at least one top electrode provided on the at least one elastic device; and at least one bottom electrode located beneath the at least one elastic device such that an initial capacitance is generated between the at least one top and bottom electrodes, wherein the drive/sense circuitry, proof-mass, supporting structure, and the at least one top and bottom electrodes are fabricated on the at least one semiconductor layer.

US Patent:

8629011, Jan 14, 2014

Filed:

Jun 15, 2011

Appl. No.:

13/161194

Inventors:

Brett M. Diamond - Pittsburgh PA, US
Franz Laermer - Weil der Stadt, DE
Andrew J. Doller - Sharpsburg PA, US
Michael J. Daley - Canonsburg PA, US
Phillip Sean Stetson - Wexford PA, US
John M. Muza - Venetia PA, US

Assignee:

Robert Bosch GmbH - Stuttgart

International Classification:

H01L 21/339

US Classification:

438166, 438486, 257415

Abstract:

A method of manufacturing a microphone using epitaxially grown silicon. A monolithic wafer structure is provided. A wafer surface of the structure includes poly-crystalline silicon in a first horizontal region and mono-crystalline silicon in a second horizontal region surrounding a perimeter of the first horizontal region. A hybrid silicon layer is epitaxially deposited on the wafer surface. Portions of the hybrid silicon layer that contact the poly-crystalline silicon use the poly-crystalline silicon as a seed material and portions that contact the mono-crystalline silicon use the mono-crystalline silicon as a seed material. As such, the hybrid silicon layer includes both mono-crystalline silicon and poly-crystalline silicon in the same layer of the same wafer structure. A CMOS/membrane layer is then deposited on top of the hybrid silicon layer.

US Patent:

20030044029, Mar 6, 2003

Filed:

Aug 16, 2002

Appl. No.:

10/222242

Inventors:

Kaigham Gabriel - Pittsburgh PA, US
John Neumann - Pittsburgh PA, US
Brett Diamond - Pittsburgh PA, US

International Classification:

G06F017/00
H04R003/00

US Classification:

381/111000, 700/094000, 381/117000

Abstract:

Each of a plurality of speaklets (MEMS membranes) produces a stream of clicks (discrete pulses of acoustic energy) that are summed to generate the desired soundwave. The speaklets are selected to be energized based on the value of a digital signal. The greater the significance of the bit of the digital signal, the more speaklets that are energized in response to that bit. Thus, a time-varying sound level is generated by time-varying the number of speaklets emitting clicks. Louder sound is generated by increasing the number of speaklets emitting clicks. The present invention represents a substantial advance over the prior art in that sound is generated directly from a digital signal without the need to convert the digital signal first to an analog signal for driving a diaphragm.

US Patent:

20120126346, May 24, 2012

Filed:

Nov 7, 2011

Appl. No.:

13/290905

Inventors:

Arnim Hoechst - Reutlingen, DE
Jochen Reinmuth - Reutlingen, DE
Brett Diamond - Pittsburgh PA, US

International Classification:

H01L 29/84
H01L 21/02

US Classification:

257416, 438 53, 257419, 438704, 257E21002, 257E29324

Abstract:

In a method for manufacturing a micromechanical membrane structure, a doped area is created in the front side of a silicon substrate, the depth of which doped area corresponds to the intended membrane thickness, and the lateral extent of which doped area covers at least the intended membrane surface area. In addition, in a DRIE (deep reactive ion etching) process applied to the back side of the silicon substrate, a cavity is created beneath the doped area, which DRIE process is aborted before the cavity reaches the doped area. The cavity is then deepened in a KOH etching process in which the doped substrate area functions as an etch stop, so that the doped substrate area remains as a basic membrane over the cavity.

US Patent:

20170245060, Aug 24, 2017

Filed:

May 8, 2017

Appl. No.:

15/589577

Inventors:

- Stuttgart, DE
Brett Matthew Diamond - Pittsburgh PA, US

International Classification:

H04R 19/00
B81B 7/00
H04R 19/04

Abstract:

Backplates for MEMS devices. In one embodiment, the backplate includes an interconnect layer, a first layer, a second layer and a plurality of openings. The interconnect layer includes a first side and a second side that is opposite from the first side. The first layer is coupled to the first side of the interconnect layer. The second layer is coupled to the second side of the interconnect layer. The plurality of openings are located between a first side of the backplate and a second side of the backplate.

US Patent:

20170044008, Feb 16, 2017

Filed:

Oct 31, 2016

Appl. No.:

15/339760

Inventors:

- Stuttgart, DE
Brett Diamond - Pittsburgh PA, US
Jochen Hoffmann - Reutlingen, DE

International Classification:

B81C 1/00
H04R 31/00

Abstract:

Systems and methods are disclosed for manufacturing a CMOS-MEMS device. A partial protective layer is deposited on a top surface of a layered to cover a logic region. A first partial etch is performed from the bottom side of the layered structure to form a first gap below a MEMS membrane within a MEMS region of the layered structure. A second partial etch is performed from the top side of the layered structure to remove a portion of a sacrificial layer between the MEMS membrane and a MEMS backplate within the MEMS region. The second partial etch releases the MEMS membrane so that it can move in response to pressures. The deposited partial protective layer prevents the second partial etch from etching a portion of the sacrificial layer positioned within the logic region of the layered structure and also prevents the second partial etch from damaging the CMOS logic component.