Brett E Lowe

age ~36

from Kuna, ID

Also known as:
  • Brett Eugene Lowe

Brett Lowe Phones & Addresses

  • Kuna, ID
  • Boise, ID
  • Fort Mohave, AZ
  • Mohave Valley, AZ
  • 13186 W Buttercup Ct, Boise, ID 83713

Specialities

Arbitration • Litigation
Name / Title
Company / Classification
Phones & Addresses
Brett Lowe
BRETT LOWE MECHANICAL, INC

Resumes

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Brett Lowe

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Brett Lowe Photo 2

Brett Lowe

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Brett Lowe

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Brett Lowe Photo 4

Brett Lowe

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Amazon

Clever Advertising: Getting The Most From Your Advertising Dollar

Clever Advertising: Getting the Most from Your Advertising Dollar

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Sticker on front


Author
Brett William Lowe

Binding
Paperback

Pages
160

Publisher
Business & Professional Pub

ISBN #
1875680063

EAN Code
9781875680061

ISBN #
1

Lawyers & Attorneys

Brett Lowe Photo 5

Brett Lowe - Lawyer

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Specialties:
Arbitration
Litigation
ISLN:
923283238
Admitted:
2012
Law School:
University of Virginia School of Law, JD

Us Patents

  • Non-Oxidizing Spacer Densification Method For Manufacturing Semiconductor Devices

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  • US Patent:
    6849510, Feb 1, 2005
  • Filed:
    Sep 22, 2003
  • Appl. No.:
    10/667919
  • Inventors:
    Brett D. Lowe - Boise ID, US
    John A. Smythe - Boise ID, US
    Timothy K. Carns - Meridian ID, US
  • Assignee:
    ZiLOG, Inc. - San Jose CA
  • International Classification:
    H01L 218234
  • US Classification:
    438275, 257351
  • Abstract:
    Non-oxidizing spacer densification method for producing semiconductor devices, such as MOSFET devices, and that may be implemented during semiconductor fabrication with little or substantially no polycide adhesion loss experienced during spacer densification. The method may be implemented to provide good polycide adhesion characteristics with reduced process complexity over conventional methods by eliminating the need for additional process steps such as metal silicide encapsulation or polysilicon surface treatments.
  • Esd Protection Transistor

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  • US Patent:
    7508038, Mar 24, 2009
  • Filed:
    Apr 29, 2005
  • Appl. No.:
    11/118680
  • Inventors:
    John A. Ransom - Nampa ID, US
    Brett D. Lowe - Boise ID, US
    Michael J. Westphal - Boise ID, US
  • Assignee:
    ZiLOG, Inc. - San Jose CA
  • International Classification:
    H01L 23/62
  • US Classification:
    257360, 257355, 257356, 257362, 257363, 257E29014
  • Abstract:
    An electrostatic discharge (ESD) transistor structure includes a self-aligned outrigger less than 0. 4 microns from a gate electrode that is 50 microns wide. The outrigger is fabricated on ordinary logic transistors of an integrated circuit without severely affecting the performance of the transistors. The outrigger is used as an implant blocking structure to form first and second drain regions on either side of a lightly doped region that underlies the outrigger. The self-aligned outrigger and the lightly doped region beneath it are used to move the location of avalanche breakdown upon an ESD event away from the channel region. Durability is extended when fewer “hot carrier” electrons accumulate in the gate oxide. A current of at least 100 milliamperes can flow into the drain and then through the ESD transistor structure for a period of more than 30 seconds without causing a catastrophic failure of the ESD transistor structure.
  • Esd Protection Transistor

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  • US Patent:
    7807528, Oct 5, 2010
  • Filed:
    Mar 24, 2009
  • Appl. No.:
    12/383534
  • Inventors:
    John A. Ransom - Nampa ID, US
    Brett D. Lowe - Boise ID, US
    Michael J. Westphal - Boise ID, US
  • Assignee:
    ZiLOG, Inc. - San Jose CA
  • International Classification:
    H01L 21/8234
  • US Classification:
    438238, 438382, 438197, 438199, 257360, 257362, 257355, 257356
  • Abstract:
    An electrostatic discharge (ESD) transistor structure includes a self-aligned outrigger less than 0. 4 microns from a gate electrode that is 50 microns wide. The outrigger is fabricated on ordinary logic transistors of an integrated circuit without severely affecting the performance of the transistors. The outrigger is used as an implant blocking structure to form first and second drain regions on either side of a lightly doped region that underlies the outrigger. The self-aligned outrigger and the lightly doped region beneath it are used to move the location of avalanche breakdown upon an ESD event away from the channel region. Durability is extended when fewer “hot carrier” electrons accumulate in the gate oxide. A current of at least 100 milliamperes can flow into the drain and then through the ESD transistor structure for a period of more than 30 seconds without causing a catastrophic failure of the ESD transistor structure.
  • Esd Protection Transistor

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  • US Patent:
    7927944, Apr 19, 2011
  • Filed:
    Sep 10, 2010
  • Appl. No.:
    12/807669
  • Inventors:
    John A. Ransom - Nampa ID, US
    Brett D. Lowe - Boise ID, US
    Michael J. Westphal - Boise ID, US
  • Assignee:
    IXYS CH GmbH
  • International Classification:
    H01L 21/8234
  • US Classification:
    438238, 438382, 438199, 257260, 257263
  • Abstract:
    An electrostatic discharge (ESD) transistor structure includes a self-aligned outrigger less than 0. 4 microns from a gate electrode that is 50 microns wide. The outrigger is fabricated on ordinary logic transistors of an integrated circuit without severely affecting the performance of the transistors. The outrigger is used as an implant blocking structure to form first and second drain regions on either side of a lightly doped region that underlies the outrigger. The self-aligned outrigger and the lightly doped region beneath it are used to move the location of avalanche breakdown upon an ESD event away from the channel region. Durability is extended when fewer “hot carrier” electrons accumulate in the gate oxide. A current of at least 100 milliamperes can flow into the drain and then through the ESD transistor structure for a period of more than 30 seconds without causing a catastrophic failure of the ESD transistor structure.
  • Esd Protection Transistor

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  • US Patent:
    8062941, Nov 22, 2011
  • Filed:
    Apr 2, 2011
  • Appl. No.:
    13/065940
  • Inventors:
    John A. Ransom - Nampa ID, US
    Brett D. Lowe - Boise ID, US
    Michael J. Westphal - Boise ID, US
  • Assignee:
    IXYS CH GmbH
  • International Classification:
    H01L 21/8238
  • US Classification:
    438199, 438200, 438238, 438382, 257355, 257356, 257360
  • Abstract:
    An electrostatic discharge (ESD) transistor structure includes a self-aligned outrigger less than 0. 4 microns from a gate electrode that is 50 microns wide. The outrigger is fabricated on ordinary logic transistors of an integrated circuit without severely affecting the performance of the transistors. The outrigger is used as an implant blocking structure to form first and second drain regions on either side of a lightly doped region that underlies the outrigger. The self-aligned outrigger and the lightly doped region beneath it are used to move the location of avalanche breakdown upon an ESD event away from the channel region. Durability is extended when fewer “hot carrier” electrons accumulate in the gate oxide. A current of at least 100 milliamperes can flow into the drain and then through the ESD transistor structure for a period of more than 30 seconds without causing a catastrophic failure of the ESD transistor structure.
  • Esd Protection Transistor

    view source
  • US Patent:
    8093121, Jan 10, 2012
  • Filed:
    Sep 29, 2011
  • Appl. No.:
    13/248520
  • Inventors:
    John A. Ransom - Nampa ID, US
    Brett D. Lowe - Boise ID, US
    Michael J. Westphal - Boise ID, US
  • Assignee:
    IXYS CH GmbH
  • International Classification:
    H01L 21/8238
  • US Classification:
    438199, 438197, 438224, 438303
  • Abstract:
    An electrostatic discharge (ESD) transistor structure includes a self-aligned outrigger less than 0. 4 microns from a gate electrode that is 50 microns wide. The outrigger is fabricated on ordinary logic transistors of an integrated circuit without severely affecting the performance of the transistors. The outrigger is used as an implant blocking structure to form first and second drain regions on either side of a lightly doped region that underlies the outrigger. The self-aligned outrigger and the lightly doped region beneath it are used to move the location of avalanche breakdown upon an ESD event away from the channel region. Durability is extended when fewer “hot carrier” electrons accumulate in the gate oxide. A current of at least 100 milliamperes can flow into the drain and then through the ESD transistor structure for a period of more than 30 seconds without causing a catastrophic failure of the ESD transistor structure.
  • Integrated Circuit Devices And Methods Of Forming Memory Array And Peripheral Circuitry Isolation

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  • US Patent:
    8461016, Jun 11, 2013
  • Filed:
    Oct 7, 2011
  • Appl. No.:
    13/268066
  • Inventors:
    James Mathew - Boise ID, US
    Brett D. Lowe - Boise ID, US
    Yunjun Ho - Boise ID, US
    H. Jim Fulford - Meridian ID, US
    Jie Sun - Boise ID, US
    Zhaoli Sun - Lehi UT, US
  • Assignee:
    Micron Technology, Inc. - Boise ID
  • International Classification:
    H01L 21/76
  • US Classification:
    438427, 438435, 438436, 257E21548
  • Abstract:
    A method of forming memory array and peripheral circuitry isolation includes chemical vapor depositing a silicon dioxide-comprising liner over sidewalls of memory array circuitry isolation trenches and peripheral circuitry isolation trenches formed in semiconductor material. Dielectric material is flowed over the silicon dioxide-comprising liner to fill remaining volume of the array isolation trenches and to form a dielectric liner over the silicon dioxide-comprising liner in at least some of the peripheral isolation trenches. The dielectric material is furnace annealed at a temperature no greater than about 500 C. The annealed dielectric material is rapid thermal processed to a temperature no less than about 800 C. A silicon dioxide-comprising material is chemical vapor deposited over the rapid thermal processed dielectric material to fill remaining volume of said at least some peripheral isolation trenches. Other aspects are disclosed, including integrated circuitry resulting from the disclosed methods and integrated circuitry independent of method of manufacture.
  • Integrated Circuit Devices And Methods Of Forming Memory Array And Peripheral Circuitry Isolation

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  • US Patent:
    8575716, Nov 5, 2013
  • Filed:
    May 14, 2013
  • Appl. No.:
    13/893454
  • Inventors:
    Brett D. Lowe - Boise ID, US
    Yunjun Ho - Boise ID, US
    H. Jim Fulford - Meridian ID, US
    Jie Sun - Boise ID, US
    Zhaoli Sun - Lehi UT, US
  • Assignee:
    Micron Technology, Inc. - Boise ID
  • International Classification:
    H01L 21/70
  • US Classification:
    257510, 257513, 257E2902
  • Abstract:
    A method of forming memory array and peripheral circuitry isolation includes chemical vapor depositing a silicon dioxide-comprising liner over sidewalls of memory array circuitry isolation trenches and peripheral circuitry isolation trenches formed in semiconductor material. Dielectric material is flowed over the silicon dioxide-comprising liner to fill remaining volume of the array isolation trenches and to form a dielectric liner over the silicon dioxide-comprising liner in at least some of the peripheral isolation trenches. The dielectric material is furnace annealed at a temperature no greater than about 500 C. The annealed dielectric material is rapid thermal processed to a temperature no less than about 800 C. A silicon dioxide-comprising material is chemical vapor deposited over the rapid thermal processed dielectric material to fill remaining volume of said at least some peripheral isolation trenches. Other aspects are disclosed, including integrated circuitry resulting from the disclosed methods and integrated circuitry independent of method of manufacture.

Plaxo

Brett Lowe Photo 6

Brett Lowe

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Cape Town, South AfricaeMarketing Manager at Shoprite

News

'Blues Brothers' Helped Revive Mandeville Mardi Gras Season Krewe

'Blues Brothers' helped revive Mandeville Mardi Gras season krewe

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  • Some of the organization's stalwart members discussed reforming the krewe in 2013 and 2014, but those efforts proved fruitless and the parade never got off the ground. Former captain, Brett Lowe, died two years ago, further hindering the efforts.
  • Date: Feb 04, 2016
  • Category: Entertainment
  • Source: Google

Flickr

Myspace

Brett Lowe Photo 15

Brett Lowe

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Locality:
PITTSBURG, CALIFORNIA
Gender:
Male
Birthday:
1947
Brett Lowe Photo 16

Brett Lowe

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Locality:
Austin, Texas
Gender:
Male
Birthday:
1938
Brett Lowe Photo 17

Brett Lowe

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Locality:
BARTOW, Florida
Gender:
Male
Birthday:
1941
Brett Lowe Photo 18

Brett Lowe

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Locality:
salisburru north, South Australia
Gender:
Male
Birthday:
1948
Brett Lowe Photo 19

Brett Lowe

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Locality:
LEMOORE, California
Gender:
Male
Birthday:
1941
Brett Lowe Photo 20

Brett Lowe

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Locality:
THE DOTTE, Michigan
Gender:
Male
Birthday:
1948

Googleplus

Brett Lowe Photo 21

Brett Lowe

Work:
Oil and Gas (E&P ) (2008)
Education:
Oklahoma State University - Fire & Emergency Management Admin
Brett Lowe Photo 22

Brett Lowe

Work:
Saint Elizabeth Regional Medical Center - Porter (2011)
Education:
University of Nebraska–Lincoln - Marketing
Brett Lowe Photo 23

Brett Lowe

Brett Lowe Photo 24

Brett Lowe

Brett Lowe Photo 25

Brett Lowe

About:
SEO is really a powerful method to boost your business; however, creating backlinks for SEO is really a difficult task if you do it by yourself. If you find this hard for you, we are a group of SEO pr...
Tagline:
Search Engine Optimization
Brett Lowe Photo 26

Brett Lowe

Brett Lowe Photo 27

Brett Lowe

Brett Lowe Photo 28

Brett Lowe

Classmates

Brett Lowe Photo 29

Brett Archer (Lowe)

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Schools:
Jackson Heights High School Holton KS 1985-1989
Brett Lowe Photo 30

Brett Lowe

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Schools:
Maple Hill High School Castleton-on-hudson NY 1987-1991
Community:
Thomas Turner, Rocky Medina
Brett Lowe Photo 31

Brett Lowe

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Schools:
Prairie Ridge High School Crystal Lake IL 1995-1999
Community:
Lauren Selcke
Brett Lowe Photo 32

Brett Lowe

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Schools:
Aubrey High School Aubrey TX 1982-1986
Community:
Jeff Goodger, Amyjo Ayers, Jay Brown, Beth Hensley, Kara Yoakum, Shane Cardwell
Brett Lowe Photo 33

Brett Lowe

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Schools:
Aubrey High School Aubrey TX 1982-1986
Community:
Jeff Goodger, Amyjo Ayers, Jay Brown, Beth Hensley, Kara Yoakum, Shane Cardwell
Brett Lowe Photo 34

Brett Lowe

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Schools:
North Star Middle School Lincoln NE 2001-2005
Community:
Brandon Snyder, Joshua Roberts, Brad Korber, Jayme Sullivan, Tasha Roberts, Ashley Marreel, Mia Lee, Brandy Koll, Alex Fall, Kaylyn Slama, Melissa Baker
Brett Lowe Photo 35

Aubrey High School, Aubre...

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Graduates:
Brett Lowe (1982-1986),
Jason Inman (1990-1994),
Jon McNabb (2001-2005),
Darlene Vandergriff (1973-1976)
Brett Lowe Photo 36

Prairie Ridge High School...

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Graduates:
Brett Lowe (1995-1999),
Virginia Mason (2000-2004),
Haggie Heckter (1992-1996),
Elizabeth Williams (1999-2003)

Youtube

BRETT LOWE 1996

Brett Lowe in the EFBB Leamington Spa 1996 contest.

  • Duration:
    1m 55s

VOICES | Brett Lowe | Day 27

Thank you for joining us for our 28 day journey of VOICES! We've asked...

  • Duration:
    4m 33s

Brett Lowe

Brett Lowe plays a piano solo at church.

  • Duration:
    5m 15s

TCGC August 2018 Practical Pistol - Brett Lowe

TCGC August 2018 Practical Pistol Special Thanks to our Team Sponsors ...

  • Duration:
    54s

Brett Eldredge & Meghan Trainor Perform 'Isla...

Sail away with us to another world with this #CMTcrossroads performanc...

  • Duration:
    4m 28s

Derby Nov 22 mash up

  • Duration:
    43m 55s

Facebook

Brett Lowe Photo 37

Brett Lowe

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Brett Lowe Photo 38

Brett Keith Lowe

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Brett Lowe Photo 39

Brett Lowe

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Brett Lowe

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Brett Lowe Photo 41

Brett Lowe

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Brett Lowe

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Brett Lowe

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Brett Lowe

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Get Report for Brett E Lowe from Kuna, ID, age ~36
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