Brett D. Lowe - Boise ID, US John A. Smythe - Boise ID, US Timothy K. Carns - Meridian ID, US
Assignee:
ZiLOG, Inc. - San Jose CA
International Classification:
H01L 218234
US Classification:
438275, 257351
Abstract:
Non-oxidizing spacer densification method for producing semiconductor devices, such as MOSFET devices, and that may be implemented during semiconductor fabrication with little or substantially no polycide adhesion loss experienced during spacer densification. The method may be implemented to provide good polycide adhesion characteristics with reduced process complexity over conventional methods by eliminating the need for additional process steps such as metal silicide encapsulation or polysilicon surface treatments.
John A. Ransom - Nampa ID, US Brett D. Lowe - Boise ID, US Michael J. Westphal - Boise ID, US
Assignee:
ZiLOG, Inc. - San Jose CA
International Classification:
H01L 23/62
US Classification:
257360, 257355, 257356, 257362, 257363, 257E29014
Abstract:
An electrostatic discharge (ESD) transistor structure includes a self-aligned outrigger less than 0. 4 microns from a gate electrode that is 50 microns wide. The outrigger is fabricated on ordinary logic transistors of an integrated circuit without severely affecting the performance of the transistors. The outrigger is used as an implant blocking structure to form first and second drain regions on either side of a lightly doped region that underlies the outrigger. The self-aligned outrigger and the lightly doped region beneath it are used to move the location of avalanche breakdown upon an ESD event away from the channel region. Durability is extended when fewer “hot carrier” electrons accumulate in the gate oxide. A current of at least 100 milliamperes can flow into the drain and then through the ESD transistor structure for a period of more than 30 seconds without causing a catastrophic failure of the ESD transistor structure.
An electrostatic discharge (ESD) transistor structure includes a self-aligned outrigger less than 0. 4 microns from a gate electrode that is 50 microns wide. The outrigger is fabricated on ordinary logic transistors of an integrated circuit without severely affecting the performance of the transistors. The outrigger is used as an implant blocking structure to form first and second drain regions on either side of a lightly doped region that underlies the outrigger. The self-aligned outrigger and the lightly doped region beneath it are used to move the location of avalanche breakdown upon an ESD event away from the channel region. Durability is extended when fewer “hot carrier” electrons accumulate in the gate oxide. A current of at least 100 milliamperes can flow into the drain and then through the ESD transistor structure for a period of more than 30 seconds without causing a catastrophic failure of the ESD transistor structure.
John A. Ransom - Nampa ID, US Brett D. Lowe - Boise ID, US Michael J. Westphal - Boise ID, US
Assignee:
IXYS CH GmbH
International Classification:
H01L 21/8234
US Classification:
438238, 438382, 438199, 257260, 257263
Abstract:
An electrostatic discharge (ESD) transistor structure includes a self-aligned outrigger less than 0. 4 microns from a gate electrode that is 50 microns wide. The outrigger is fabricated on ordinary logic transistors of an integrated circuit without severely affecting the performance of the transistors. The outrigger is used as an implant blocking structure to form first and second drain regions on either side of a lightly doped region that underlies the outrigger. The self-aligned outrigger and the lightly doped region beneath it are used to move the location of avalanche breakdown upon an ESD event away from the channel region. Durability is extended when fewer “hot carrier” electrons accumulate in the gate oxide. A current of at least 100 milliamperes can flow into the drain and then through the ESD transistor structure for a period of more than 30 seconds without causing a catastrophic failure of the ESD transistor structure.
An electrostatic discharge (ESD) transistor structure includes a self-aligned outrigger less than 0. 4 microns from a gate electrode that is 50 microns wide. The outrigger is fabricated on ordinary logic transistors of an integrated circuit without severely affecting the performance of the transistors. The outrigger is used as an implant blocking structure to form first and second drain regions on either side of a lightly doped region that underlies the outrigger. The self-aligned outrigger and the lightly doped region beneath it are used to move the location of avalanche breakdown upon an ESD event away from the channel region. Durability is extended when fewer “hot carrier” electrons accumulate in the gate oxide. A current of at least 100 milliamperes can flow into the drain and then through the ESD transistor structure for a period of more than 30 seconds without causing a catastrophic failure of the ESD transistor structure.
John A. Ransom - Nampa ID, US Brett D. Lowe - Boise ID, US Michael J. Westphal - Boise ID, US
Assignee:
IXYS CH GmbH
International Classification:
H01L 21/8238
US Classification:
438199, 438197, 438224, 438303
Abstract:
An electrostatic discharge (ESD) transistor structure includes a self-aligned outrigger less than 0. 4 microns from a gate electrode that is 50 microns wide. The outrigger is fabricated on ordinary logic transistors of an integrated circuit without severely affecting the performance of the transistors. The outrigger is used as an implant blocking structure to form first and second drain regions on either side of a lightly doped region that underlies the outrigger. The self-aligned outrigger and the lightly doped region beneath it are used to move the location of avalanche breakdown upon an ESD event away from the channel region. Durability is extended when fewer “hot carrier” electrons accumulate in the gate oxide. A current of at least 100 milliamperes can flow into the drain and then through the ESD transistor structure for a period of more than 30 seconds without causing a catastrophic failure of the ESD transistor structure.
Integrated Circuit Devices And Methods Of Forming Memory Array And Peripheral Circuitry Isolation
James Mathew - Boise ID, US Brett D. Lowe - Boise ID, US Yunjun Ho - Boise ID, US H. Jim Fulford - Meridian ID, US Jie Sun - Boise ID, US Zhaoli Sun - Lehi UT, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 21/76
US Classification:
438427, 438435, 438436, 257E21548
Abstract:
A method of forming memory array and peripheral circuitry isolation includes chemical vapor depositing a silicon dioxide-comprising liner over sidewalls of memory array circuitry isolation trenches and peripheral circuitry isolation trenches formed in semiconductor material. Dielectric material is flowed over the silicon dioxide-comprising liner to fill remaining volume of the array isolation trenches and to form a dielectric liner over the silicon dioxide-comprising liner in at least some of the peripheral isolation trenches. The dielectric material is furnace annealed at a temperature no greater than about 500 C. The annealed dielectric material is rapid thermal processed to a temperature no less than about 800 C. A silicon dioxide-comprising material is chemical vapor deposited over the rapid thermal processed dielectric material to fill remaining volume of said at least some peripheral isolation trenches. Other aspects are disclosed, including integrated circuitry resulting from the disclosed methods and integrated circuitry independent of method of manufacture.
Integrated Circuit Devices And Methods Of Forming Memory Array And Peripheral Circuitry Isolation
Brett D. Lowe - Boise ID, US Yunjun Ho - Boise ID, US H. Jim Fulford - Meridian ID, US Jie Sun - Boise ID, US Zhaoli Sun - Lehi UT, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 21/70
US Classification:
257510, 257513, 257E2902
Abstract:
A method of forming memory array and peripheral circuitry isolation includes chemical vapor depositing a silicon dioxide-comprising liner over sidewalls of memory array circuitry isolation trenches and peripheral circuitry isolation trenches formed in semiconductor material. Dielectric material is flowed over the silicon dioxide-comprising liner to fill remaining volume of the array isolation trenches and to form a dielectric liner over the silicon dioxide-comprising liner in at least some of the peripheral isolation trenches. The dielectric material is furnace annealed at a temperature no greater than about 500 C. The annealed dielectric material is rapid thermal processed to a temperature no less than about 800 C. A silicon dioxide-comprising material is chemical vapor deposited over the rapid thermal processed dielectric material to fill remaining volume of said at least some peripheral isolation trenches. Other aspects are disclosed, including integrated circuitry resulting from the disclosed methods and integrated circuitry independent of method of manufacture.
Some of the organization's stalwart members discussed reforming the krewe in 2013 and 2014, but those efforts proved fruitless and the parade never got off the ground. Former captain, Brett Lowe, died two years ago, further hindering the efforts.
Oklahoma State University - Fire & Emergency Management Admin
Brett Lowe
Work:
Saint Elizabeth Regional Medical Center - Porter (2011)
Education:
University of Nebraska–Lincoln - Marketing
Brett Lowe
Brett Lowe
Brett Lowe
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