Brett A Smith

US Patent:

6719387, Apr 13, 2004

Filed:

Jul 22, 2002

Appl. No.:

10/200718

Inventors:

Md Abidur Rahman - Allen TX
Brett E. Smith - McKinney TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

B41J 2938

US Classification:

347 5, 327389

Abstract:

An improved inkjet print head driver. The driver includes a source of predrive charge for a first, drive transistor coupled by its source and drain between an output node and a power supply, and having its gate coupled to the source of predrive charge. A second transistor is provided, adapted to receive an input signal at its gate. A third, control transistor is coupled by its source and drain between the gate of the first transistor and the second transistor, the second transistor being coupled by its source and drain between the third transistor and ground. Optionally, a resistor is coupled in parallel with the third transistor, i. e. , across the source and drain of the third transistor.

US Patent:

6952120, Oct 4, 2005

Filed:

Feb 12, 2004

Appl. No.:

10/777991

Inventors:

MD Abidur Rahman - Allen TX, US
William E. Grose - Plano TX, US
Brett E. Smith - McKinney TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03B001/00

US Classification:

327108, 327103, 327427

Abstract:

The present invention provides a system () for controlling drive signal timing parameters of an output driver circuit (). The present invention defines a driver circuit having an output interface (), and a first transistor () coupled to a first voltage supply (), a first control signal (), and a first node (). The circuit also has a first resistive element, coupled between the first node and a second node (). A second resistive element () is coupled to ground. A second transistor () is coupled to the second node, to a second control signal (), and the second resistive element. The circuit has a third transistor (), coupled to the first and second nodes, and to a third node (). A third resistive element () is coupled between the third node and the output interface. A fourth transistor () is coupled to the first and third nodes, and to the output interface. The circuit also has a fifth transistor (), coupled to a second voltage supply (), to the first node, and to the output interface.

US Patent:

7035071, Apr 25, 2006

Filed:

Dec 29, 2004

Appl. No.:

11/025706

Inventors:

Kee Chee Tiew - Richardson TX, US
Thomas A. Schmidt - Murphy TX, US
Brett E. Smith - McKinney TX, US
John C. Vogt - Denton TX, US
Abidur Rahman - Allen TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H02H 9/08

US Classification:

361 939, 700 33

Abstract:

A switching regulator having a current limit with adaptive cycle skipping. A buck type switching regulator circuit is provided, including an energy storage component, such as an inductor or capacitor, and a switch for controllably providing an input current to the energy storage component. A control unit controls the on time and the off time of the switch by providing cyclically recurring control pulses to the switch that cause the switch to be on during the pulses and off otherwise. A current monitor circuit monitors a current corresponding to the input current applied to the energy storage component during the periodic control pulses. An overcurrent signal generator generates an overcurrent signal pulse upon detection of the monitored current at a level above a predetermined level corresponding to an overcurrent condition. A state machine responds to the overcurrent signal pulse and suppresses a number of the cyclically recurring control pulses, thereby controlling the period between the recurring control pulses that are not suppressed, in accordance with a predetermined algorithm that increases the number each time an overcurrent signal pulse is detected in successive periods.

US Patent:

7236003, Jun 26, 2007

Filed:

Sep 29, 2005

Appl. No.:

11/239021

Inventors:

Shanmuganand Chellamuthu - Richardson TX, US
Brett E. Smith - McKinney TX, US
Thomas A. Schmidt - Murphy TX, US
Abidur Rahman - Allen TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 19/007

US Classification:

326 14, 326 27, 363 50

Abstract:

The H-bridge circuit with shoot through current prevention during power-up includes: a high side transistor; a low side transistor coupled in series with the high side transistor; pull down devices coupled to a control node of the high side transistor and to a control node of the low side transistor; and wherein the pull down devices are controlled by a pull down circuit including a Power On Reset circuit, monitoring the digital power supply such that the high side and low side transistors are OFF until the digital power supply has settled to a desired operating voltage.

US Patent:

7511527, Mar 31, 2009

Filed:

Jan 29, 2008

Appl. No.:

12/021931

Inventors:

Kee Chee Tiew - Richardson TX, US
Brett Smith - McKinney TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G01R 31/26

US Classification:

324769, 324763, 324765

Abstract:

Methods and apparatus to test power transistors of integrated circuits on a wafer are disclosed. An example method comprises measuring a drain-source on resistance of a first transistor, measuring a drain-source on resistance of a second transistor, computing a scaling ratio between the transistors based on the drain-source on resistances of the transistors, measuring a first current indicative of an over-current condition of the first transistor, and computing a second current of the second transistor based on the current of the second transistor and the scaling ratio.

US Patent:

7560972, Jul 14, 2009

Filed:

Jan 29, 2008

Appl. No.:

12/021939

Inventors:

Kee Chee Tiew - Richardson TX, US
Brett Smith - McKinney TX, US
Abidur Rahman - Allen TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03L 5/00

US Classification:

327333, 326 81

Abstract:

Methods and apparatus to reduce propagation delay of circuits are disclosed. A disclosed apparatus to reduce propagation delay of a circuit comprises a level shifter to selectively turn a first circuit on and off; a first switch to couple the first circuit to a second circuit when the first circuit is on, wherein the second circuit is to selectively receive a first current from the first circuit based on a signal the second circuit receives from the level shifter; and a second switch to couple the first circuit to a reference signal based on the first current, the second switch causing the first circuit to start to turn off.

US Patent:

7719245, May 18, 2010

Filed:

Nov 8, 2007

Appl. No.:

11/937282

Inventors:

Huijuan Li - Plano TX, US
Md Abidur Rahman - Allen TX, US
Brett E. Smith - McKinney TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G05F 1/44
G05F 1/56

US Classification:

323282, 323284, 323285, 323351

Abstract:

Methods and apparatus for a self-tracking high-side pre-driver control are described. In an example, a method is described comprising charging a first terminal associated with a first capacitive element to a first voltage with respect to ground and a second terminal associated with a second capacitive element to a second voltage with respect to ground, changing the first voltage and the second voltage with respect to ground by changing a swing voltage, selecting one of the first voltage or the second voltage based on a first switched-mode power supply topology or a second switched-mode power supply topology and driving a transistor using the selected voltage.

US Patent:

7868599, Jan 11, 2011

Filed:

Nov 26, 2007

Appl. No.:

11/986775

Inventors:

Md Abidur Rahman - Allen TX, US
Huijuan Li - Plano TX, US
Brett E. Smith - Mckinney TX, US
Zheng Li - Farmers Branch TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G05F 1/00

US Classification:

323282, 323288

Abstract:

In a method and system for sensing current in a switching regulator (SWR) operating in a current mode, a power switch is coupled to receive the current from a switching element, the power switch being controlled by a gate signal. An inrush of the current causes an initial transient spike (ITS). A buffer having a buffer input and a buffer output is coupled to receive the gate signal and provide a buffered gate signal. The buffer output is disabled during the ITS. A sense switch (SW) is coupled to receive a portion of the current from the switching element, the SW being turned on by the buffered gate signal after the initial transient spike. A sense resistor (SR) is coupled to receive the portion of the current from the SW. An amplifier converts the portion of the current through the SR to a voltage signal for controlling the SWR.