Brian Scott Allison

US Patent:

6615334, Sep 2, 2003

Filed:

Dec 27, 2000

Appl. No.:

09/748982

Inventors:

Brian David Allison - Rochester MN
Scott D. Clark - Rochester MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1314

US Classification:

711170, 711135

Abstract:

A method and apparatus are provided for implementing input/output IO data management with an I/O buffer (IOB) directory in a compressed memory subsystem. Processor and I/O commands destined for a system memory are identified. I/O cacheline stores are accumulated in a free area of memory until a full block of data is received with only a directory to the data maintained on a memory controller chip. Then a pointer swap is provided to replace the existing compression block.

US Patent:

7694055, Apr 6, 2010

Filed:

Oct 15, 2005

Appl. No.:

11/251334

Inventors:

Ryuji Orita - Redmond WA, US
Susumu Arai - Portland OR, US
Brian D. Allison - Rochester MN, US
Patrick M. Bland - Raleigh NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/24

US Classification:

710260, 710261, 710262, 710263, 710264, 710265, 710266, 710267, 710268, 710269, 710240

Abstract:

Interrupts are directed to currently idle processors. Which of a number of processors of a computing system that are currently idle is determined. An interrupt is received and directed to one of the currently idle processors for processing. Determining which processors are currently idle can be accomplished by monitoring each processor to determine whether it has entered an idle state. When a processor has entered an idle state, it is thus determined that the processor is currently idle. Where just one processor is currently idle, an interrupt is directed to this processor. Where more than one processor is currently idle, one of these processors is selected to which to deliver an interrupt, such as in a round-robin manner. Where no processor is currently idle, then one of the processors is selected to which to deliver an interrupt.

US Patent:

7761669, Jul 20, 2010

Filed:

Jul 10, 2007

Appl. No.:

11/775459

Inventors:

Brian David Allison - Rochester MN, US
Wayne Barrett - Rochester MN, US
Joseph Allen Kirscht - Rochester MN, US
Elizabeth A. McGlone - Rochester MN, US
Brian T. Vanderpool - Byron MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00
G06F 13/18

US Classification:

711151, 711105, 710 6

Abstract:

A memory controller receives read requests from a processor into a read queue. The memory controller dynamically modifies an order of servicing the requests based on how many pending requests are in the read queue. When the read queue is relatively empty, requests are serviced oldest first to minimize latency. When the read queue becomes progressively fuller, requests are progressively, using three or more memory access modes, serviced in a manner that increases throughput on a memory bus to reduce the likelihood that the read queue will become full and further requests from the processor would have to be halted.

US Patent:

7793034, Sep 7, 2010

Filed:

Nov 5, 2007

Appl. No.:

11/934974

Inventors:

Brian D. Allison - Rochester MN, US
Joseph A. Kirscht - Rochester MN, US
Elizabeth A. McGlone - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711 5, 711201, 711202, 711217

Abstract:

In a method of translating a physical memory address to a device address in a device memory space, a fast address translate of the physical memory address, adapted to translate addresses in uniformly configured device memory space, is performed thereby generating a first translated address. A full address translate of the physical memory address, adapted to translate addresses in non-uniformly configured device memory space, is also performed thereby generating a second translated address. Boundaries of a uniform portion of the device memory space are identified, to which the physical memory address is compared to determine if the physical memory address is in the uniform portion of the device memory space. When the physical memory address is in the uniform portion, the first translated address is selected as the device address. Otherwise, the second translated address is selected.

US Patent:

7882314, Feb 1, 2011

Filed:

Sep 7, 2007

Appl. No.:

11/851487

Inventors:

Brian David Allison - Rochester MN, US
Joseph Allen Kirscht - Rochester MN, US
Elizabeth A. McGlone - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00
G06F 13/00
G06F 13/28
G06F 11/00
G11C 29/00

US Classification:

711158, 711167, 714 42, 714718

Abstract:

A method and apparatus to efficiently scrub a memory, during a scrub period, of a computer system that has a memory comprising a number of memory elements. Examples of memory elements are memory ranks and banks. A memory rank may further comprise one or more banks. The computer system has a memory controller that receives read requests and write requests from a processor. The memory controller includes a scrub controller configured to output more than one scrub request during a particular request selector cycle. The memory controller includes a request selector that services a read request, a write request, or one of the scrub requests during a request selector cycle.

US Patent:

7882323, Feb 1, 2011

Filed:

Sep 7, 2007

Appl. No.:

11/851458

Inventors:

Brian David Allison - Rochester MN, US
Joseph Allen Kirscht - Rochester MN, US
Elizabeth A. McGlone - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00
G06F 13/00
G06F 13/28
G06F 11/00
G11C 29/00

US Classification:

711167, 714 42, 714718

Abstract:

A method and apparatus to scrub a memory during a scrub period, of a computer system. The computer system has a memory controller that receives read requests and write requests from a processor. The memory controller provides a different priority for scrub requests versus read requests during a period of relatively light memory workload versus a period of relatively heavy workload. The memory controller provides a relatively higher priority for scrub requests near an end of a scrub period if scrub progress is behind an expected scrub progress.

US Patent:

8001354, Aug 16, 2011

Filed:

Apr 27, 2007

Appl. No.:

11/741049

Inventors:

Brian David Allison - Rochester MN, US
Joseph Allen Kirscht - Rochester MN, US
Elizabeth A. McGlone - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/02

US Classification:

711170, 711171, 711173

Abstract:

A computer system, computer program product, and method implement dynamic physical memory reallocation. A system management interface (SMI) Handler and an Operating System (OS) are arranged for exchanging communications. Periodically the SMI Handler queries the operating system to identify a percentage of available memory currently being utilized. Responsive to the identified percentage of available memory currently being utilized, physical memory is dynamically reallocated.

US Patent:

20020073287, Jun 13, 2002

Filed:

Dec 12, 2000

Appl. No.:

09/735411

Inventors:

Brian Allison - Rochester MN, US
Scott Clark - Rochester MN, US
Joseph Kirscht - Rochester MN, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION

International Classification:

G06F012/12

US Classification:

711/159000, 711/207000, 711/156000

Abstract:

A method and apparatus are provided for implementing locking of non-data page operations in a memory system. In the method for implementing locking of non-data page operations of the invention, checking for a look aside buffer invalidate request is performed. Responsive to identifying a look aside buffer invalidate request, a real address is locked for the look aside buffer invalidate request. Then checking for a non-data page operation is performed. Responsive to identifying a non-data page operation, checking for the non-data page operation to complete is performed. Responsive to identifying the completed non-data page operation, the real address is unlocked for the look aside buffer invalidate request. Only a lock is placed on the page for a non-data page operation. A look aside buffer invalidate sequence is not performed for the non-data page operation.