Brian E Campbell

Address:

16892 E Hialeah Ave, Aurora, CO 80015

VIN:

5NMSG73D99H302055

Make:

HYUNDAI

Model:

SANTA FE

Year:

2009

US Patent:

6418488, Jul 9, 2002

Filed:

Apr 23, 2001

Appl. No.:

09/840422

Inventors:

Kendell Alan Chilton - Marlboro MA
Miklos Sandorfi - Foxboro MA
Brian K. Campbell - Marlboro MA

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F 1300

US Classification:

710 20, 710 22, 710 52, 710 62, 710 64, 710104, 710129, 710131, 711149, 711150, 711169, 712225

Abstract:

A plurality of state machines arranged into three functional units, an Upper Machine, Middle Machine and a Lower Machine facilitate movement of user data between a buffer memory and a Global Memory (GM) in a data transfer interface. The Middle Machine controls all data movement to and from the GM. Although not directly in the data path, it is responsible for coordinating control between elements that comprise data transfer channels. The Middle Machine is interconnected to and provides control and coordination between the Upper and Lower sides of the buffer memory. The Lower Machine connects to a data assembly mechanism of each pipe. The Upper Machine connects to the backplane, which in turn connects to Global Memory. The actual data transfers between the buffer memory and GM are controlled by the Upper Machine, and transfers between the buffer memory and the data assembly mechanism are controlled by the Lower Machine.

US Patent:

6839750, Jan 4, 2005

Filed:

Mar 3, 2001

Appl. No.:

09/798571

Inventors:

Andreas L. Bauer - Maynard MA, US
Russell R. Laporte - Webster MA, US
Richard J. Nordin - Worcester MA, US
Brian G. Campbell - Holden MA, US

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F 1540

US Classification:

709223, 707103 R, 707103, 709218, 709252

Abstract:

There is disclosed a system, method, apparatus and computer program product for managing a storage system including a SAN within a computer network. The storage system can be managed in object-oriented computer language. Object trees of each component in the storage system or SAN are obtained and combined on each storage processor in the storage system. The user interface (UI) can therefore select one storage processor within the storage system, and request such combined object tree information for the entire storage system or SAN from only that singular storage processor on which such combined information is stored. This eliminates a severe computational drain on the UI, which otherwise would be required to make these object tree combinations, and further allows a single point of storage management contact between UI and storage system or SAN by way of that singular storage or portal processor. Commands from the UI destined for any node within the storage system or SAN are thus always addressed to that same single point of contact or portal processor allowing for ease of use and other advantages.

US Patent:

6981111, Dec 27, 2005

Filed:

Mar 31, 2003

Appl. No.:

10/403263

Inventors:

Ofer Porat - Westborough MA, US
Brian K. Campbell - Milford MA, US
Jane Xu - Franklin MA, US
Eric J. Bruno - Marlborough MA, US

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F012/00

US Classification:

711154, 711156

Abstract:

A system and method are provided for transferring data appended with a tag indicating whether the transmit data is data allowed to be re-transmitted or inhibited from being re-transmitted to a memory section. A buffer is fed with the transmit data from a data source for transmit data to the memory section. A receiver is receives data from the memory section and checks such received data for errors. Either the transmit data from the data source is coupled to the memory section in absence of a detected error or the data in the buffer is coupled to the memory section when an error has been detected and the data has been tagged with an indication that the transmit data is data allowed to be re-transmitted; selectively.

US Patent:

7124179, Oct 17, 2006

Filed:

Oct 13, 2004

Appl. No.:

10/964090

Inventors:

Andreas L. Bauer - Maynard MA, US
Russell R. Laporte - Webster MA, US
Richard J. Nordin - Worcester MA, US
Brian G. Campbell - Holden MA, US

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F 15/40

US Classification:

709223, 707103 R, 707103, 709218, 709252

Abstract:

There is disclosed a system, method, apparatus and computer program product for managing a storage system including a SAN within a computer network. The storage system can be managed in object-oriented computer language. Object trees of each component in the storage system or SAN are obtained and combined on each storage processor in the storage system. The user interface (UI) can therefore select one storage processor within the storage system, and request such combined object tree information for the entire storage system or SAN from only that singular storage processor on which such combined information is stored. This eliminates a severe computational drain on the UI, which otherwise would be required to make these object tree combinations, and further allows a single point of storage management contact between UI and storage system or SAN by way of that singular storage or portal processor. Commands from the UI destined for any node within the storage system or SAN are thus always addressed to that same single point of contact or portal processor allowing for ease of use and other advantages.

US Patent:

7143306, Nov 28, 2006

Filed:

Mar 31, 2003

Appl. No.:

10/403262

Inventors:

Ofer Porat - Westborough MA, US
Brian K. Campbell - Milford MA, US
Jane Xu - Franklin MA, US
Eric J. Bruno - Marlborough MA, US
Paul C. Wilson - Mendon MA, US

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F 11/00

US Classification:

714 5, 710 37, 710 38

Abstract:

A system interface having a cache memory and a plurality of directors. Each one of the plurality of directors includes a data pipe coupled between an input of such one of the directors. The data pipe includes a data pipe memory and a data pipe memory controller for controlling the data pipe memory. Each one of the directors includes microprocessor coupled to the data pipe memory controller. The system includes a switching network coupled to the cache memory to transfer data between the memory and: (a) the input of a selected one of the plurality of directors through the data pipe memory; (b) the microprocessor and the data pipe memory through the data pipe memory controller of a selected one of the plurality of directors; and (c) the microprocessor and the data pipe memory controller while by-passing the data pipe memory of a selected one of the plurality of directors.

US Patent:

7272668, Sep 18, 2007

Filed:

Jun 26, 2003

Appl. No.:

10/606872

Inventors:

John K. Walton - Mendon MA, US
Ofer Porat - Westborough MA, US
Christopher S. MacLellan - Walpole MA, US
Daniel Castel - Boston MA, US
Kendell A. Chilton - Southborough MA, US
Brian K. Campbell - Milford MA, US
Gregory S. Robidoux - Westboro MA, US
Brian D. Magnuson - Somerville MA, US

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F 3/00
G06F 13/00
G06F 13/42
G06F 11/00

US Classification:

710 15, 710 33, 710 36, 710105, 714 5, 714 43, 714 47

Abstract:

A system having a plurality of printed circuit broads each one having an electrical component thereon. A backplane carries a signal indicative of a performance characteristic of the electrical components on the plurality of printed circuit boards plugged into such backplane. The performance characteristic may be, for example component speed, operating protocol, etc. System start-up is interrupted upon detection of such incompatibility. After start up, upon plugging an additional printed circuit broad having an electrical component thereon with an operating incompatible with the electrical components on the plurality of printed circuit boards into the backplane, the electrical component on such additional printed circuit will not be electrically coupled to the electrical component on the additional printed circuit board from the electrical components of the plurality of printed circuit boards.

US Patent:

7275201, Sep 25, 2007

Filed:

Apr 13, 2005

Appl. No.:

11/104735

Inventors:

Ofer Porat - Westborough MA, US
James Tryhubczak - Cumberland RI, US
Brian K. Campbell - Cedar Park TX, US
Clayton A. Curry - Waltham MA, US

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

H03M 13/00

US Classification:

714767, 714773

Abstract:

A system having memory modules for storing nibbles of a word. The nibbles include an error correction/detection code. A memory controller is response to clock pulses to produce a read command. A synchronizer is responsive to the read nibbles and an associated read strobe signal for synchronizing the read nibbles and the read strobes to the clock pulses. A detection section is responsive to the clock pulses and the read command for producing a time window representative of a time duration during which each of the read strobes is expected. The detection system is responsive to each one of the read strobes and the produced time window for producing, for each one of the read strobes, a corresponding one of a plurality of NIBBLE ERROR signals. Each one of the NIBBLE ERROR signals indicates whether the corresponding one of the read strobes is within the produced window or is absent from such window.

US Patent:

7574555, Aug 11, 2009

Filed:

Mar 18, 2005

Appl. No.:

11/083571

Inventors:

Ofer Porat - Westborough MA, US
Brian K. Campbell - Cedar Park TX, US
Brian D. Magnuson - Somerville MA, US
Stephen Scaringella - Holliston MA, US

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F 12/00
G06F 12/02
G06F 13/00
G06F 13/28

US Classification:

711105, 711 1

Abstract:

A memory system having a plurality of sets of memory modules. The system includes a plurality of sets of memory controllers, each one of the memory controllers being coupled to a corresponding one of the plurality of sets of memory modules. The system includes a port for providing address and read/write control signals to the memory system. The memory controllers are interconnected in a daisy chain arrangement to the port.